Advertisement

A Survey of Computing Architectures

  • Somnath Paul
  • Swarup Bhunia
Chapter
  • 811 Downloads

Abstract

In this chapter, we review the computing architectures popularly used in commercial systems. This includes general-purpose processors, graphics processing units and FPGAs. Motivated by the fact that hardware reconfigurable frameworks like FPGAs can significantly benefit energy-efficiency for compute-intensive workloads, we then discuss some well-known hardware reconfigurable architectures. Finally we discuss the scaling challenges for fully-spatial reconfigurable architectures such as FPGAs.

Keywords

Single Instruction Multiple Data Logic Block Reconfigurable System Host Processor Critical Path Delay 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    [Online], “The Landscape of Parallel Computing Research: A View From Berkeley”. http://view.eecs.berkeley.edu/wiki/Main_Page
  2. 2.
    F. Pollack, “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies”, in Intl. Symp. on Microarchitecture, 1999Google Scholar
  3. 3.
    E.S. Chung, P.A. Milder, J.C. Hoe, K. Mai, “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? in Intl. Symp. on Microarchitecture, 2010Google Scholar
  4. 4.
    K. Compton, S. Hauck, “Reconfigurable computing: a survey of systems and software”. ACM Comput. Surv. 34(2), 171–210 (2002)CrossRefGoogle Scholar
  5. 5.
    R. Hartenstein, “A Decade of Reconfigurable Computing: A Visionary Retrospective”, in DATE, 2001Google Scholar
  6. 6.
    K. Eguro, S. Hauck, “Resource allocation for coarse-grain FPGA development”. IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 24(10), 1572–1581 (2005)CrossRefGoogle Scholar
  7. 7.
    V. Betz, J. Rose, A. Marquardt, “Architecture and CAD for Deep-Submicron FPGA”. (Springer, Heidelberg, 1999)CrossRefGoogle Scholar
  8. 8.
    A. Dehon, “DPGA Utilization and Application”, in Intl. Symp. on FPGAs, 1996Google Scholar
  9. 9.
    C. Ebeling, D.C. Cronquist, P. Franklin, “RaPiD - Reconfigurable Pipelined Datapath”, in Intl. Workshop on Field-Programmable Logic and Applications, 1996Google Scholar
  10. 10.
    S. Hauck, T.W. Fry, M.M. Hosler, J.P. Kao, “The Chimaera reconfigurable functional unit”. IEEE Trans. Very Large Scale Integrat. Syst. 12(2), 206–217 (2004)CrossRefGoogle Scholar
  11. 11.
    E. Mirsky, A. Dehon, “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources”, in FPGAs for Custom Computing Machines, 1996Google Scholar
  12. 12.
    S.C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R.R. Taylor, R. Laufer, “PipeRench: A Coprocessor for Streaming Multimedia Acceleration”, in Intl. Symp. on Computer Architecture, 1999Google Scholar
  13. 13.
    C. Brunelli, F. Garzia, J. Nurmi, “A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities”. J. Real Time Image Process. 3(1), 21–32 (2006)Google Scholar
  14. 14.
  15. 15.
    R. Razdan, M.D. Smith, “A High-Performance Microarchitecture with Hardware-Programmable Functional Units”, in Intl. Symp. on Microarchitecture, 1994Google Scholar
  16. 16.
    T. Miyamori, K. Olukotun, “REMARC: Reconfigurable Multimedia Array Coprocessor”, in Intl. Symp. on FPGAs, 1998Google Scholar
  17. 17.
    R.D. Wittig, P. Chow, “OneChip: An FPGA Processor with Reconfigurable Logic”, in FPGAs for Custom Computing Machines, 1996Google Scholar
  18. 18.
    J. Babb et al., “The RAW Benchmark Suite: Computation Structures for General Purpose Computing”, in FPGAs for Custom Computing Machines, 1997Google Scholar
  19. 19.
    M. Gokhale et al., “SPLASH: A Reconfigurable Linear Logic Array”, in Intl. Conference on Parallel Processing, 1990Google Scholar
  20. 20.
    J.R. Hauser, J. Wawrzynek, “Garp: a MIPS Processor with a Reconfigurable Coprocessor”, in FPGAs for Custom Computing Machines, 1997Google Scholar
  21. 21.
    D. Chen, J. Rabaey, “Reconfigurable multi-processor IC for rapid prototyoing of algorithm-specific high-speed datapaths”. IEEE J. Solid State Circ. 27(12), 1895–1904 (1992)CrossRefGoogle Scholar
  22. 22.
    [Online], “Tensilica’s Xtensa customizable processors”. http://www.tensilica.com/products/xtensa-customizable.htm
  23. 23.
    [Online], “Stretch: Software Configurable Processors”. http://www.stretchinc.com/
  24. 24.
    H. Singh, M. Lee, G. Lu, F.J. Kurdahi, N. Bagherzadeh, E.M. Chaves Filho, “MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications”. IEEE Trans. Comput. 49(5), 465–481 (2000)CrossRefGoogle Scholar
  25. 25.
    F. Barat, R. Lauwereins, G. Deconinck, “Reconfigurable instruction set processors from a hardware/software perspective”. IEEE Trans. Softw. Eng. 28(9), 847–862 (2002)CrossRefGoogle Scholar
  26. 26.
    T. Mudge, “Power: a first-class architectural design constraint”. IEEE Comput. 34(4), 52–58 (2001)CrossRefGoogle Scholar
  27. 27.
    I. Kuon, J. Rose, “Measuring the gap between FPGAs and ASICs”. IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 26(2), 203–215 (2007)CrossRefGoogle Scholar
  28. 28.
    L. Shang, A.S. Kaviani, K. Bathala, “Dynamic Power Consumption in VirtexTM-II FPGA Family”, in Intl. Symp. on FPGAs, 2002Google Scholar
  29. 29.
    T. Tuan, B. Lai, “Leakage Power Analysis of a 90nm FPGA”, in Custom Integrated Circuits Conf., 2003Google Scholar
  30. 30.
    F. Li, Y. Lin, L. He, “Field programmability of supply voltages for FPGA power reduction”. IEEE Trans. Comput. Aided Des. Intgerat. Circ. Syst. 26(4), 752–764 (2007)CrossRefGoogle Scholar
  31. 31.
    F. Li, Y. Lin, L. He, J. Cong, “Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics”, in Intl. Symp. on FPGAs, 2004Google Scholar
  32. 32.
    J.H. Anderson, F.N. Najm, “Low-Power Programmable Routing Circuitry for FPGAs”, in ICCAD, 2004Google Scholar
  33. 33.
    A. Gayasen et al., “Reducing Leakage Energy in FPGAs Using Region-Constrained Placement”, in Intl. Symp. on FPGAs, 2004Google Scholar
  34. 34.
    Y. Lin, F. Li, L. He, “Routing Track Duplication with Fine-Grained Power-Gating for FPGA Interconnect Power Reduction”, in ASP-DAC, 2005Google Scholar
  35. 35.
    S. Das, A.P. Chandrakasan, A. Rahman, R. Reif, “Wiring requirement and three-dimensional integration technology for field programmable gate arrays”. IEEE Trans. Very Large Scale Integrat. Syst., 11(1), 44–54 (2003)CrossRefGoogle Scholar
  36. 36.
    [Online], “Predictive Technology Model”. http://ptm.asu.edu/
  37. 37.
    [Online], “Improving FPGA Performance and Area Using an Adaptive Logic Module”. www.altera.com/literature/cp/cp-01004.pdf
  38. 38.
    [Online], “ITRS 2007: Interconnect”. http://www.itrs.net/links/2007itrs/home2007.htm
  39. 39.
    G. Lemieux, D. Lewis, “Circuit Design of Routing Switches”, in Intl. Symp. on FPGAs, 2002Google Scholar
  40. 40.
    S. Paul, F. Cai, X. Zhang, S. Bhunia, “Reliability-driven ECC allocation for multiple bit error resilience in processor cache”. IEEE Trans. Comput. 60(1), 20–34 (2011)MathSciNetCrossRefGoogle Scholar
  41. 41.
    S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Y. Xie, M.J. Irwin, “Improving Soft-Error Tolerance of FPGA Configuration Bits”, in ICCAD, 2004Google Scholar
  42. 42.
    Y. Lin, L. He, M. Hutton, “Stochastic physical synthesis considering prerouting interconnect uncertainty and process variation for FPGAs”. IEEE Trans. Very Large Scale Integrat. Syst. 16(2), 80–88 (2008)Google Scholar
  43. 43.
    [Online], “FPGAs Provide Reconfigurable DSP Solutions”. www.altera.com/literature/wp/wp_dsp_fpga.pdf
  44. 44.
    [Online], “DSP Co-Processing in FPGAs: Embedding High-Performance, Low-Cost DSP Functions”. www.xilinx.com/support/documentation/white_papers/wp212.pdf
  45. 45.
    L. Cheng, P. Wong, F. Li, Y. Lin, L. He, “Device and Architecture Cooptimization for FPGA Power Reduction”, in DAC, 2005Google Scholar
  46. 46.
    J. Rose, R.J. Francis, D. Lewis, P. Chow, “Architecture of field programmable gate arrays: The effect of logic functionality on area efficiency”. IEEE J. Solid State Circ. 25(5), 1217–1225 (1990)CrossRefGoogle Scholar
  47. 47.
    E. Ahmed, J. Rose, “The effect of LUT and cluster size on deep submicron FPGA performance and density”. IEEE Trans. Very Large Scale Integrat. Syst. 12(3), 288–298 (2004)CrossRefGoogle Scholar
  48. 48.
    A. Sharma, K. Compton, C. Ebeling, S. Hauck, “Exploration of Pipelined FPGA Interconnect Structures”, in Intl. Symp. on FPGAs, 2004Google Scholar
  49. 49.
    [Online], “Achronix Semiconductor Corp.” http://www.achronix.com/
  50. 50.
    V. Betz, J. Rose, “FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density”, in Intl. Symp. on FPGAs, 1999Google Scholar
  51. 51.
    [Online], “Error Detection and Recovery Using CRC in Altera FPGA Devices”. http://www.altera.com/literature/an/an357.pdf
  52. 52.
    S.P. Park, D. Lee, K. Roy, “Soft-error-resilient FPGAs using Built-2-D hamming product code”. IEEE Trans. Very Large Scale Integrat. Syst., 248–256 (2011)Google Scholar
  53. 53.
    D. Chen, J. Cong, Y. Fan, “Low-Power High-Level Synthesis for FPGA Architectures”, in ISLPED, 2003Google Scholar
  54. 54.
    V.K. Prasanna, “Energy-efficient computations on FPGAs”. J. Supercomput. 32(2), 139–162 (2005)CrossRefGoogle Scholar
  55. 55.
    Y. Hu, Y. Lin, L. He, T. Tuan, “Physical synthesis for FPGA interconnect power reduction by dual-vdd budgeting and retiming”. ACM Trans. Des. Autom. Electron. Syst. 13(2), 1–29 (2008)CrossRefGoogle Scholar
  56. 56.
    [Online], “Stratix IV FPGA ALM Logic Structure’s 8-Input Fracturable LUT”. http://www.altera.com/products/devices/stratix-fpgas/stratix-iv/overvie%w/architecture/stxiv-alm-logic-structure.htmlGoogle Scholar
  57. 57.
    [Online], “VPR and T-VPack 5.0.2 Full CAD Flow for Heterogeneous FPGAs”. http://www.eecg.utoronto.ca/vpr/
  58. 58.
    M.A. Abdul-Aziz, M.B. Tahoori, “Soft Error Reliability Aware Placement and Routing for FPGAs”, in ITC, 2010Google Scholar
  59. 59.
    S. Golshan, E. Bozorgzadeh, “Single-Event-Upset (SEU) Awareness in FPGA Routing”, in DAC, 2007Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

Personalised recommendations