Abstract
In this chapter, we review the computing architectures popularly used in commercial systems. This includes general-purpose processors, graphics processing units and FPGAs. Motivated by the fact that hardware reconfigurable frameworks like FPGAs can significantly benefit energy-efficiency for compute-intensive workloads, we then discuss some well-known hardware reconfigurable architectures. Finally we discuss the scaling challenges for fully-spatial reconfigurable architectures such as FPGAs.
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References
[Online], “The Landscape of Parallel Computing Research: A View From Berkeley”. http://view.eecs.berkeley.edu/wiki/Main_Page
F. Pollack, “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies”, in Intl. Symp. on Microarchitecture, 1999
E.S. Chung, P.A. Milder, J.C. Hoe, K. Mai, “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? in Intl. Symp. on Microarchitecture, 2010
K. Compton, S. Hauck, “Reconfigurable computing: a survey of systems and software”. ACM Comput. Surv. 34(2), 171–210 (2002)
R. Hartenstein, “A Decade of Reconfigurable Computing: A Visionary Retrospective”, in DATE, 2001
K. Eguro, S. Hauck, “Resource allocation for coarse-grain FPGA development”. IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 24(10), 1572–1581 (2005)
V. Betz, J. Rose, A. Marquardt, “Architecture and CAD for Deep-Submicron FPGA”. (Springer, Heidelberg, 1999)
A. Dehon, “DPGA Utilization and Application”, in Intl. Symp. on FPGAs, 1996
C. Ebeling, D.C. Cronquist, P. Franklin, “RaPiD - Reconfigurable Pipelined Datapath”, in Intl. Workshop on Field-Programmable Logic and Applications, 1996
S. Hauck, T.W. Fry, M.M. Hosler, J.P. Kao, “The Chimaera reconfigurable functional unit”. IEEE Trans. Very Large Scale Integrat. Syst. 12(2), 206–217 (2004)
E. Mirsky, A. Dehon, “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources”, in FPGAs for Custom Computing Machines, 1996
S.C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R.R. Taylor, R. Laufer, “PipeRench: A Coprocessor for Streaming Multimedia Acceleration”, in Intl. Symp. on Computer Architecture, 1999
C. Brunelli, F. Garzia, J. Nurmi, “A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities”. J. Real Time Image Process. 3(1), 21–32 (2006)
[Online], “The Kress ALU Array”. http://xputers.informatik.uni-kl.de/faq-pages/kressalu.html
R. Razdan, M.D. Smith, “A High-Performance Microarchitecture with Hardware-Programmable Functional Units”, in Intl. Symp. on Microarchitecture, 1994
T. Miyamori, K. Olukotun, “REMARC: Reconfigurable Multimedia Array Coprocessor”, in Intl. Symp. on FPGAs, 1998
R.D. Wittig, P. Chow, “OneChip: An FPGA Processor with Reconfigurable Logic”, in FPGAs for Custom Computing Machines, 1996
J. Babb et al., “The RAW Benchmark Suite: Computation Structures for General Purpose Computing”, in FPGAs for Custom Computing Machines, 1997
M. Gokhale et al., “SPLASH: A Reconfigurable Linear Logic Array”, in Intl. Conference on Parallel Processing, 1990
J.R. Hauser, J. Wawrzynek, “Garp: a MIPS Processor with a Reconfigurable Coprocessor”, in FPGAs for Custom Computing Machines, 1997
D. Chen, J. Rabaey, “Reconfigurable multi-processor IC for rapid prototyoing of algorithm-specific high-speed datapaths”. IEEE J. Solid State Circ. 27(12), 1895–1904 (1992)
[Online], “Tensilica’s Xtensa customizable processors”. http://www.tensilica.com/products/xtensa-customizable.htm
[Online], “Stretch: Software Configurable Processors”. http://www.stretchinc.com/
H. Singh, M. Lee, G. Lu, F.J. Kurdahi, N. Bagherzadeh, E.M. Chaves Filho, “MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications”. IEEE Trans. Comput. 49(5), 465–481 (2000)
F. Barat, R. Lauwereins, G. Deconinck, “Reconfigurable instruction set processors from a hardware/software perspective”. IEEE Trans. Softw. Eng. 28(9), 847–862 (2002)
T. Mudge, “Power: a first-class architectural design constraint”. IEEE Comput. 34(4), 52–58 (2001)
I. Kuon, J. Rose, “Measuring the gap between FPGAs and ASICs”. IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 26(2), 203–215 (2007)
L. Shang, A.S. Kaviani, K. Bathala, “Dynamic Power Consumption in VirtexTM-II FPGA Family”, in Intl. Symp. on FPGAs, 2002
T. Tuan, B. Lai, “Leakage Power Analysis of a 90nm FPGA”, in Custom Integrated Circuits Conf., 2003
F. Li, Y. Lin, L. He, “Field programmability of supply voltages for FPGA power reduction”. IEEE Trans. Comput. Aided Des. Intgerat. Circ. Syst. 26(4), 752–764 (2007)
F. Li, Y. Lin, L. He, J. Cong, “Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics”, in Intl. Symp. on FPGAs, 2004
J.H. Anderson, F.N. Najm, “Low-Power Programmable Routing Circuitry for FPGAs”, in ICCAD, 2004
A. Gayasen et al., “Reducing Leakage Energy in FPGAs Using Region-Constrained Placement”, in Intl. Symp. on FPGAs, 2004
Y. Lin, F. Li, L. He, “Routing Track Duplication with Fine-Grained Power-Gating for FPGA Interconnect Power Reduction”, in ASP-DAC, 2005
S. Das, A.P. Chandrakasan, A. Rahman, R. Reif, “Wiring requirement and three-dimensional integration technology for field programmable gate arrays”. IEEE Trans. Very Large Scale Integrat. Syst., 11(1), 44–54 (2003)
[Online], “Predictive Technology Model”. http://ptm.asu.edu/
[Online], “Improving FPGA Performance and Area Using an Adaptive Logic Module”. www.altera.com/literature/cp/cp-01004.pdf
[Online], “ITRS 2007: Interconnect”. http://www.itrs.net/links/2007itrs/home2007.htm
G. Lemieux, D. Lewis, “Circuit Design of Routing Switches”, in Intl. Symp. on FPGAs, 2002
S. Paul, F. Cai, X. Zhang, S. Bhunia, “Reliability-driven ECC allocation for multiple bit error resilience in processor cache”. IEEE Trans. Comput. 60(1), 20–34 (2011)
S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Y. Xie, M.J. Irwin, “Improving Soft-Error Tolerance of FPGA Configuration Bits”, in ICCAD, 2004
Y. Lin, L. He, M. Hutton, “Stochastic physical synthesis considering prerouting interconnect uncertainty and process variation for FPGAs”. IEEE Trans. Very Large Scale Integrat. Syst. 16(2), 80–88 (2008)
[Online], “FPGAs Provide Reconfigurable DSP Solutions”. www.altera.com/literature/wp/wp_dsp_fpga.pdf
[Online], “DSP Co-Processing in FPGAs: Embedding High-Performance, Low-Cost DSP Functions”. www.xilinx.com/support/documentation/white_papers/wp212.pdf
L. Cheng, P. Wong, F. Li, Y. Lin, L. He, “Device and Architecture Cooptimization for FPGA Power Reduction”, in DAC, 2005
J. Rose, R.J. Francis, D. Lewis, P. Chow, “Architecture of field programmable gate arrays: The effect of logic functionality on area efficiency”. IEEE J. Solid State Circ. 25(5), 1217–1225 (1990)
E. Ahmed, J. Rose, “The effect of LUT and cluster size on deep submicron FPGA performance and density”. IEEE Trans. Very Large Scale Integrat. Syst. 12(3), 288–298 (2004)
A. Sharma, K. Compton, C. Ebeling, S. Hauck, “Exploration of Pipelined FPGA Interconnect Structures”, in Intl. Symp. on FPGAs, 2004
[Online], “Achronix Semiconductor Corp.” http://www.achronix.com/
V. Betz, J. Rose, “FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density”, in Intl. Symp. on FPGAs, 1999
[Online], “Error Detection and Recovery Using CRC in Altera FPGA Devices”. http://www.altera.com/literature/an/an357.pdf
S.P. Park, D. Lee, K. Roy, “Soft-error-resilient FPGAs using Built-2-D hamming product code”. IEEE Trans. Very Large Scale Integrat. Syst., 248–256 (2011)
D. Chen, J. Cong, Y. Fan, “Low-Power High-Level Synthesis for FPGA Architectures”, in ISLPED, 2003
V.K. Prasanna, “Energy-efficient computations on FPGAs”. J. Supercomput. 32(2), 139–162 (2005)
Y. Hu, Y. Lin, L. He, T. Tuan, “Physical synthesis for FPGA interconnect power reduction by dual-vdd budgeting and retiming”. ACM Trans. Des. Autom. Electron. Syst. 13(2), 1–29 (2008)
[Online], “Stratix IV FPGA ALM Logic Structure’s 8-Input Fracturable LUT”. http://www.altera.com/products/devices/stratix-fpgas/stratix-iv/overvie%w/architecture/stxiv-alm-logic-structure.html
[Online], “VPR and T-VPack 5.0.2 Full CAD Flow for Heterogeneous FPGAs”. http://www.eecg.utoronto.ca/vpr/
M.A. Abdul-Aziz, M.B. Tahoori, “Soft Error Reliability Aware Placement and Routing for FPGAs”, in ITC, 2010
S. Golshan, E. Bozorgzadeh, “Single-Event-Upset (SEU) Awareness in FPGA Routing”, in DAC, 2007
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Paul, S., Bhunia, S. (2014). A Survey of Computing Architectures. In: Computing with Memory for Energy-Efficient Robust Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-7798-3_2
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DOI: https://doi.org/10.1007/978-1-4614-7798-3_2
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