Mitigating the Effect of Parametric Failures in MBC Frameworks

  • Somnath Paul
  • Swarup Bhunia


Since MBC uses large, high-density memories for computation, reliable operation of the framework under increasing process variations becomes a major concern. Variation may potentially cause memory access failures or flipping of stored data during read-out (Mukhopadhyay et al., IEEE Trans Comput Aided Des Integrated Circ Syst 24(12), 2005), which leads to incorrect execution of the mapped application. Moreover, in order to reduce the power requirement, memory core is conventionally operated at lower supply voltages. Although this minimizes the active and leakage power consumption, read and access failure probabilities increase significantly at low operating voltages (Mukhopadhyay et al., IEEE Trans Comput Aided Des Integrated Circ Syst 24(12), 2005). In order to address variation induced memory failures in the MBC framework, it’s read dominant behavior can be exploited since write to the MBC framework only occurs occasionally during reconfiguration. Exploiting the read-dominant memory access pattern in MBC, a preferential memory cell sizing approach is proposed to make the memory more robust to read and access failures. The resultant decrease in write stability is addressed by low-overhead circuit techniques during reconfiguration.


Discrete Cosine Transform Memory Cell Preferential Mapping Memory Block Delay Constraint 
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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

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