Background and Motivation
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This chapter describes the Von-Neumann bottleneck and its effect in limiting the energy-efficiency of traditional compute hardware for processing data-intensive applications. For these applications, traditional approach of bringing data from off-chip memory to on-chip compute engines has been demonstrated to be ineffective in terms of energy-efficiency. In the era of big data, on-chip computing is restricted by both off-chip bandwidth and access energy. In such a scenario, an off-chip compute framework realized by instrumenting non-volatile memory can prove to be an effective solution in mitigating the Von-Neumann bottleneck. This chapter also discusses the nature of such an off-chip compute hardware and the applications which can benefit from it.
KeywordsData-intensive Applications Local DRAM Limited Data Transfer Rate Host Processor Software Execution Model
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