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Preferential Memory Design for MBC Frameworks

  • Somnath Paul
  • Swarup Bhunia
Chapter
  • 727 Downloads

Abstract

Since memory is primarily used for computation in a memory based reconfigurable framework, memory access is dominated by read rather than write, which occurs only during the process of application mapping. For a given technology, optimizing a memory cell for both read and write pose contradictory requirements (Mukhopadhyay et al., IEEE Trans Comput Aided Des Integrated Circ Syst 24(12), 2005). However, exploiting the read-dominated memory access pattern in reconfigurable frameworks, it is possible to come up with a novel memory cell design which offers better read power and performance at the cost of increased write power and performance. Dense memory arrays with such a memory cell would therefore offer better energy efficiency. Details of these circuit-level optimizations corresponding to CMOS based SRAM technology and emerging STTRAM technology are provided in this chapter. This chapter also presents circuit techniques which skew the memory cells be more energy-efficient when storing logic “0” rather than logic “1”. Application mapping heuristics are presented which can leverage this asymmetric memory behavior for further improving the energy-efficiency of the applications mapped to the MBC framework.

Keywords

Mapping Heuristic Read Operation Memory Array Magnetic Tunneling Junction SRAM Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

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