Preferential Memory Design for MBC Frameworks

  • Somnath Paul
  • Swarup Bhunia


Since memory is primarily used for computation in a memory based reconfigurable framework, memory access is dominated by read rather than write, which occurs only during the process of application mapping. For a given technology, optimizing a memory cell for both read and write pose contradictory requirements (Mukhopadhyay et al., IEEE Trans Comput Aided Des Integrated Circ Syst 24(12), 2005). However, exploiting the read-dominated memory access pattern in reconfigurable frameworks, it is possible to come up with a novel memory cell design which offers better read power and performance at the cost of increased write power and performance. Dense memory arrays with such a memory cell would therefore offer better energy efficiency. Details of these circuit-level optimizations corresponding to CMOS based SRAM technology and emerging STTRAM technology are provided in this chapter. This chapter also presents circuit techniques which skew the memory cells be more energy-efficient when storing logic “0” rather than logic “1”. Application mapping heuristics are presented which can leverage this asymmetric memory behavior for further improving the energy-efficiency of the applications mapped to the MBC framework.


Mapping Heuristic Read Operation Memory Array Magnetic Tunneling Junction SRAM Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    S. Paul, S. Chatterjee, S. Mukhopadhyay, S. Bhunia, “A Circuit-Software Co-design Approach for Improving EDP in Reconfigurable Frameworks”, in IEEE/ACM Intl. Conference on Computer-Aided Design (ICCAD), 109–112 (2009)Google Scholar
  2. 2.
    L. Chang et al., “Stable SRAM Cell Design for the 32nm Node and Beyond”, in Symp. on VLSI Technology, 2005Google Scholar
  3. 3.
    J. Singh, J. Mathew, S.P. Mohanty, D.K. Pradhan, “Single Ended Static Random Access Memory for Low-Vdd High-Speed Embedded Systems”, in VLSI Design, 2009Google Scholar
  4. 4.
    J. Cong, S. Xu, “Technology Mapping for FPGAs with Embedded Memory Blocks”, in Intl. Symp. on FPGAs, 1998Google Scholar
  5. 5.
    S.J.E. Wilton, “SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays”, in Intl. Symp. on FPGAs, 1998Google Scholar
  6. 6.
    J. Cong, S. Xu, “Performance-driven technology mapping for heterogeneous FPGAs”. IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 19(11), 1268–1281 (2000)CrossRefGoogle Scholar
  7. 7.
    T.W. Andre et al., “A 4-Mb 0.18-m 1T1MTJ Toggle MRAM with Balanced Three Input Sensing Scheme and Locally Mirrored Unidirectional Write Drivers”, in Intl. Solid-State Circuits Conference, 2004Google Scholar
  8. 8.
    S. Paul, S. Bhunia, “Computing with Nanoscale Memory: Model and Architecture”, in Intl. Symp on Nanoscale Architecture, 2011Google Scholar
  9. 9.
    S. Paul, S. Chatterjee, S. Mukhopadhyay, S. Bhunia, “Nanoscale Reconfigurable Computing Using Non-Volatile 2-D STTRAM Array”, in Intl. Conf. on Nanotechnology, 2009Google Scholar
  10. 10.
    [Online], “Predictive Technology Model”.
  11. 11.
    [Online], “iFAR – intelligent FPGA Architecture Repository”
  12. 12.
    S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Y. Xie, M.J. Irwin, “Improving Soft-Error Tolerance of FPGA Configuration Bits”, in ICCAD, 2004Google Scholar
  13. 13.
    J.H. Anderson, F. Najm, “Active leakage power optimization for FPGAs”. IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 25(3), (2006)Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

Personalised recommendations