Advertisement

Design Space Exploration for MBC Based Generic Reconfigurable Computing Framework

  • Somnath Paul
  • Swarup Bhunia
Chapter
  • 736 Downloads

Abstract

This chapter describes the design space exploration for a MBC based generic reconfigurable framework. Design space exploration identifies the appropriate values for several design parameters of the framework based upon the technology node, the applications being mapped and the power and performance constraints provided to the MBC software flow. To be specific, the exploration phase determines the configuration for both compute blocks (MLBs) and the programmable interconnect. For this exploration, information regarding the variation in design overhead with varying specification for individual hardware components of the MBC framework must be provided to the software flow. The MBC software flow by itself generates an exhaustive combination of all design points ensuring that at each design point a given input application can be mapped to the MBC framework. A mapping result (power and performance) is generates for each of these design points. The user may then select one of the design points based on whether power and performance is more critical to mapping the input application.

Keywords

Function Table Design Space Exploration Technology Node Benchmark Circuit Single Partition 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    M. Hansen, H. Yalcin, J. Hayes, “Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering”. IEEE Des. Test Comput. (1999)Google Scholar
  2. 2.
    [Online], “iFAR – intelligent FPGA Architecture Repository”. http://www.eecg.utoronto.ca/vpr/architectures/
  3. 3.
    [Online], “Predictive Technology Model”. http://ptm.asu.edu/
  4. 4.
    [Online], “Stratix Family of FPGAs”. www.altera.com

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

Personalised recommendations