Hardware-Based Computational Intelligence for Size, Weight, and Power Constrained Environments

  • Bryant WysockiEmail author
  • Nathan McDonald
  • Clare Thiem
  • Garrett Rose
  • Mario GomezII
Part of the Advances in Information Security book series (ADIS, volume 55)


Nanotechnology research is an enabling field and is closely aligned with advances in neuromorphic architectures, energy efficient computing, and autonomy efforts. The development of neuromorphic circuits leverages a mixture of proven CMOS technologies with experimental devices and architectures that pose significant challenges for integration and fabrication. This chapter examines the pressures pushing the development of unconventional computing designs for size, weight, and power constrained environments and briefly reviews some of the trends that are influencing the development of solid-state neuromorphic systems. Later sections provide high level examples of selected approaches to hardware design and fabrication.


Single Instruction Multiple Data 2T1M Cell Resistive Random Access Memory Threshold Logic Memristive Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    P.W. Singer, Wired for War: The Robotics Revolution and Conflict in the 21st Century (Penguin, New York, 2009)Google Scholar
  2. 2.
    W.J.A. Dahm (2012), Report on Technology horizons: a vision for air force science and technology during 2010–2030, Accessed 04 Jan 2013
  3. 3.
    J. Misra, I. Saha, Artificial neural networks in hardware: a survey of two decades of progress, J. Neurocomput. 74, 239–255 (2010) Google Scholar
  4. 4.
    D. Lammers (2012), Intel cancels Tejas, moves to dual-core designs. In EE Times. Accessed 31 Jan 2013
  5. 5.
    M.D. Hill, M.R. Marty, Amdahl’s law in the multicore era. Computer 41(7), 33–38 (2008)CrossRefGoogle Scholar
  6. 6.
    H. Esmaeilzadeh, E. Blem, R.S. Amant, K. Sankaralingam, D. Burger, Dark silicon and the end of multicore scaling, in 38th Annual International Symposium on Computer Architecture (ISCA), pp. 365–376, 4–8 June 2011Google Scholar
  7. 7.
    P.M. Kogge, Hardware Evolution Trends of Extreme Scale Computing, University of Notre Dame, 26 April 2011Google Scholar
  8. 8.
    J. Koomey, Growth in Data Center Electricity use 2005 to 2010 Analytics Press, Oakland (2011)Google Scholar
  9. 9.
  10. 10.
    Y.V. Pershin, M. Di Ventra, Adv. Phys. 60, 145–227 (2011)CrossRefGoogle Scholar
  11. 11.
    G. Snider, Prolog: Memristor Minds, in Advances in Neuromorphic Memristor Science and Applications, Springer Series in Cognitive And Neural Systems 4, ed. by R. Kozma, R. Pino, G. Pazienza (Springer, New York, 2012), pp. 3–7CrossRefGoogle Scholar
  12. 12.
    H. Ames, M. Versace et al., Persuading Computers to Act More Like Brains, in Advances in Neuromorphic Memristor Science and Applications, Springer Series in Cognitive and Neural Systems 4, ed. by R. Kozma, R. Pino, G. Pazienza (Springer, New York, 2012), pp. 37–61CrossRefGoogle Scholar
  13. 13.
    C. Yakopcic, T.M. Taha et al., Analysis of a memristor based 1T1M crossbar architecture, in The 2011 International Joint Conference on Neural Networks (IJCNN), IEEE, pp. 3243–3247 (2011)Google Scholar
  14. 14.
    D.B. Strukov, K.K. Likharev, Reconfigurable Nano-Crossbar Architectures, in Nanoelectronics and Information Technology, 3rd edn., ed. by R. Waser (Wiley, New York, 2012), pp. 543–562Google Scholar
  15. 15.
    GS. Rose, H. Manem et al., Leveraging memristive systems in the construction of digital logic circuits and architectures, in Proceedings of the IEEE , 100(6), 2033–2049 (2012)Google Scholar
  16. 16.
    J. Rajendran, H. Manem et al., An energy-efficient memristive threshold logic circuit. IEEE. Trans. Comput. 61(4), 6:1–6:22 (2012)MathSciNetCrossRefGoogle Scholar
  17. 17.
    J. Rajendran, H. Manem et al., An approach to tolerate variations for memristor based applications, in Proceedings of the 24th International Conference on VLSI Design (VLSI Design) pp. 18–23 (2011)Google Scholar
  18. 18.
    J. Rajendran, H. Manem et al., Memristor based programmable threshold logic array, in IEEE/ACM International Symposium on Nanoscale Architectures, pp. 5–10 (2010)Google Scholar
  19. 19.
    J. Rajendran, R. Karri, G.S. Rose, Parallel memristors improve variation tolerance in memristive digital circuits, in IEEE International Symposium on Circuits and Systems. pp. 2241–2244 (2011)Google Scholar
  20. 20.
    H. Manem, G.S. Rose, Design considerations for variation tolerant multilevel cmos/nano memristor memory, in ACM Great Lakes Symposium on VLSI. pp. 287–292 (2010)Google Scholar
  21. 21.
    H. Manem, G.S. Rose, A Crosstalk Minimization technique for sublithographic programmable logic arrays, in IEEE Conference on Nanotechnology. pp. 218–222 (2009)Google Scholar
  22. 22.
    H. Manem, J. Rajendran, G.S. Rose, Design Considerations for Multi-Level CMOS/Nano Memristive Memory. ACM. J. Emerg. Technol. Comput. Syst. 8(1), 1–22 (2012)CrossRefGoogle Scholar
  23. 23.
    H. Manem, G.S. Rose, A read-monitored write circuit for 1T1 M memristor memories, IEEE International Symposium on Circuits and Systems. pp. 2938–2941 (2011)Google Scholar
  24. 24.
    M. Soltiz, C. Merkel et al., RRAM-based adaptive neural logic block for implementing non-linearly separable functions, in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2012)Google Scholar
  25. 25.
    M. Solti, D. Kudithipudi et al., Submitted 2012. Single-Layer Neural Logic Blocks Using Memristive Synapses, Submitted to IEEE Transaction on Computers (2012)Google Scholar
  26. 26.
    H. Manem, J. Rajendran, G.S. Rose, Stochastic gradient descent inspired training technique for a hybrid CMOS/Nano trainable threshold gate array. IEEE. Trans. Circuits. Syst. 59(5), 1051–1060 (2012)MathSciNetCrossRefGoogle Scholar
  27. 27.
    A.R. Omondi, J.C. Rajapakse, FPGA Implementations of Neural Networks (Springer, Netherlands, 2006)CrossRefGoogle Scholar
  28. 28.
    A. Eide, T. Lindblad et al., An implementation of the zero instruction set computer (ZISC036) on a PC/ISA-bus card, in 1994 WNN/FNN (1994)Google Scholar
  29. 29.
    F.M. Dias, A. Antunes, A. Mota, Artificial Neural Networks: a Review of Commercial Hardware. Eng. Appl. Artif. Intell. IFAC 17(8), 945–952 (2004)CrossRefGoogle Scholar
  30. 30.
    The CogniMem Communique (2012) CogniMem Technologies, Inc., Folsom, 1(2).’,%20Vol%201,%20Issue%202.pdf. Accessed 31 Jan 2013
  31. 31.
  32. 32.
    Y. Q. Liu, D. Wei, N. Zhang, M.Z. Zhao Vehicle-license-plate recognition based on neural networks, in Information and Automation (ICIA), 2011 IEEE International Conference on, pp. 363–366 (2011)Google Scholar
  33. 33.
    K. Shen, C.I. Bargmann, The immunoglobin superfamily protein SYG-1 determines the location of specific synapses in C. Elegans. In Cell. 112(5), 619–630 (2003)CrossRefGoogle Scholar
  34. 34.
    K. Diefendorff, P.K. Dubey, How multimedia workloads will change processor design. In Computer 30(9), 43–45 (1997)CrossRefGoogle Scholar
  35. 35.
    R.E. Pino, G. Genello et al., Emerging neuromorphic computing architectures and enabling hardware for cognitive information processing applications. Air Force Research Lab Rome, Information Directorate (2010)Google Scholar
  36. 36.
    D. Shires, S.J. Park et al., Asymmetric core computing for US Army high-performance computing applications (No. ARL-TR-4788). Army Research Lab Aberdeen Proving Ground MD, Computational and Information Sciences Dir (2009)Google Scholar
  37. 37.
    B. Barney, Introduction to parallel computing. Lawrence. Livermore. Nat. Lab. 6(13), 10 (2010)Google Scholar
  38. 38.
    R. Zbikowski, Fly like a fly [micro-air vehicle], in Spectrum, IEEE 42(11), pp. 46–51 (2005)Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Bryant Wysocki
    • 1
    Email author
  • Nathan McDonald
    • 1
  • Clare Thiem
    • 1
  • Garrett Rose
    • 1
  • Mario GomezII
    • 2
  1. 1.Information Directorate, Air Force Research LaboratoryRomeUSA
  2. 2.Department of Engineering, Science and MathematicsState University of New York Institute of TechnologyUticaUSA

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