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Compiling for VLIW DSPs

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Handbook of Signal Processing Systems

Abstract

This chapter describes fundamental compiler techniques for VLIW DSP processors. We begin with a review of VLIW DSP architecture concepts, as far as relevant for the compiler writer. As a case study, we consider the TI TMS320C62xTMclustered VLIW DSP processor family. We survey the main tasks of VLIW DSP code generation, discuss instruction selection, cluster assignment, instruction scheduling and register allocation in some greater detail, and present selected techniques for these, both heuristic and optimal ones. Some emphasis is put on phase ordering problems and on phase coupled and integrated code generation techniques.

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Notes

  1. 1.

    Processors that decouple issue packets from fetch packets are commonly also referred to as Explicitly Parallel Instruction set Computing (EPIC) architectures.

  2. 2.

    NOP (no operation) instructions only occupy an issue slot but no further resources.

  3. 3.

    For simplicity of presentation, we assume here that write latency and read latency are constants for each instruction. In general, they may in some cases depend on run-time conditions exposed by the hardware and vary in an interval between earliest and latest write resp. read latency. See also our remarks on the LE model further below. For a more detailed latency model, we refer to Rau et al. [87].

  4. 4.

    Note that in some papers and texts, the meanings of the terms delay and latency are reversed.

  5. 5.

    Exception: For load and store instructions, two more resources are used to model load destination register resp. store source register access to the two register files, as only one loaded or stored register can be accessed per register file and clock cycle. Furthermore, load instructions can cause additional implicit delays (pipeline stalls) by unbalanced access to the internal memory banks (see later). This effect could likewise be modeled with additional resources representing the different memory banks. However, this will only be useful for predicting stalls where the alignment of the accessed memory addresses is statically known.

  6. 6.

    Even though ’C62x assembly language allows an issue packet to start in a fetch packet and continue into the next one, the assembler will automatically create and insert a fresh fetch packet after the first one, move the pending issue packet there, and fill up the remainder of the first issue packet with NOP instructions.

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Acknowledgements

The author thanks Mattias Eriksson and Dake Liu for discussions and commenting on a draft of this chapter. The author also thanks Eric Stotzer from Texas Instruments for interesting discussions about code generation for the TI ’C6x DSP processor family. This work was funded by Vetenskapsrådet (project Integrated Software Pipelining) and SSF (project DSP platform for emerging telecommunication and multimedia).

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  1. Department of Computer Science (IDA), Linköping University, 58183, Linköping, Sweden

    Christoph W. Kessler

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    Shuvra S. Bhattacharyya

  2. Leiden Inst. Advanced Computer Science, Leiden Embedded Research Center, Leiden University, Niels Bohrweg 1, Leiden, 2333 CA, Netherlands

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  3. Software for Systems on Silicon, RWTH Aachen University, Templergraben 55, Aachen, 52056, Germany

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Kessler, C.W. (2013). Compiling for VLIW DSPs. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6859-2_36

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