Skip to main content
SpringerLink
Log in

Arithmetic

  • Chapter
  • First Online:
Handbook of Signal Processing Systems

  • 6051 Accesses

Abstract

In this chapter fundamentals of arithmetic operations and number representations used in DSP systems are discussed. Different relevant number systems are outlined with a focus on fixed-point representations. Structures for accelerating the carry-propagation of addition are discussed, as well as multi-operand addition. For multiplication, different schemes for generating and accumulating partial products are presented. In addition to that, optimization for constant coefficient multiplication is discussed. Division and square-rooting are also briefly outlined. Furthermore, floating-point arithmetic and the IEEE 754 floating-point arithmetic standard are presented. Finally, some methods for computing elementary functions, e.g., trigonometric functions, are presented.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 219.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 279.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    It is worth noticing that for one’s complement the sign-bits are inserted at the LSB side.

References

  1. C. R. Baugh and B. A. Wooley, “A two’s complement parallel array multiplication algorithm,” IEEE Trans. Comput., vol. 22, pp. 1045–1047, Dec. 1973.

    Article  MATH  Google Scholar 

  2. K. Bickerstaff, M. J. Schulte, and E. E. Swartzlander, Jr., “Parallel reduced area multipliers,” J. VLSI Signal Processing, vol. 9, no. 3, pp. 181–191, Nov. 1995.

    Article  Google Scholar 

  3. R. P. Brent and H. T. Kung, “A regular layout for parallel adders,” IEEE Trans. Comput., vol. 31, pp. 260–264, Mar. 1982.

    Article  MathSciNet  MATH  Google Scholar 

  4. S. C. Chan and P. M. Yiu, “An efficient multiplierless approximation of the fast Fourier transform using sum-of-powers-of-two (SOPOT) coefficients,” IEEE Signal Processing Lett., vol. 9, no. 10, pp. 322–325, Oct. 2002.

    Article  Google Scholar 

  5. T. A. C. M. Claasen, W. F. G. Mecklenbräuker, and J. B. H. Peek, “Effects of quantization and overflow in recursive digital filters,” IEEE Trans. Acoust. Speech Signal Processing, vol. 24, no. 6, Dec. 1976.

    Google Scholar 

  6. A. Croisier, D. J. Esteban, M. E. Levilion, and V. Rizo, “Digital filter for PCM encoded signals,” U.S. Patent 3 777 130, Dec. 4, 1973.

    Google Scholar 

  7. L. Dadda, “Some schemes for parallel multipliers,” Alta Frequenza, vol. 34, pp. 349–356, May 1965.

    Google Scholar 

  8. F. de Dinechin and A. Tisserand, “Multipartite table methods,” IEEE Trans. Comput., vol. 54, no. 3, pp. 319–330, Mar. 2005.

    Article  Google Scholar 

  9. M. D. Ercegovac and T. Lang, “On-the-fly conversion of redundant into conventional representation,” IEEE Trans. Comput., vol. 36, pp. 895–897, July 1987.

    Article  Google Scholar 

  10. M. D. Ercegovac and T. Lang, Division and Square Root: Digit-Recurrence Algorithms and Implementations, Kluwer Academic Publishers, 1994.

    Google Scholar 

  11. M. D. Ercegovac and T. Lang, Digital Arithmetic, Morgan Kaufmann Publishers, 2004.

    Google Scholar 

  12. H. Eriksson, P. Larsson-Edefors, M. Sheeran, M. Själander, D. Johansson, and M. Schölin, “Multiplier reduction tree with logarithmic logic depth and regular connectivity,” in Proc. IEEE Int. Symp. Circuits Syst., 2006.

    Google Scholar 

  13. A. Fettweis, and K. Meerkötter, “On parasitic oscillations in digital filters under looped conditions,” IEEE Trans. Circuits Syst., vol. 24, no. 9, pp. 475–481, Sept. 1977.

    Google Scholar 

  14. O. Gustafsson, “A difference based adder graph heuristic for multiple constant multiplication problems,” in Proc. IEEE Int. Symp. Circuits Syst., 2007.

    Google Scholar 

  15. O. Gustafsson, “Lower bounds for constant multiplication problems,” IEEE Trans. Circuits Syst. II, vol. 54, no. 11, pp. 974–978, Nov. 2007.

    Google Scholar 

  16. O. Gustafsson and K. Johansson, “An empirical study on standard cell synthesis of elementary function look-up tables,” in Proc. Asilomar Conf. Signals Syst. Comput., 2008.

    Google Scholar 

  17. O. Gustafsson and L. Wanhammar, “Low-complexity and high-speed constant multiplications for digital filters using carry-save arithmetic” in Digital Filters, Intech, 2011.

    Google Scholar 

  18. O. Gustafsson, A. G. Dempster, K. Johansson, M. D. Macleod, and L. Wanhammar, “Simplified design of constant coefficient multipliers,” Circuits, Syst. Signal Processing, vol. 25, no. 2, pp. 225–251, Apr. 2006.

    Google Scholar 

  19. D. Harris, “A taxonomy of parallel prefix networks”, in Proc. Asilomar Conf. Signals Syst. Comput., 2003.

    Google Scholar 

  20. R. I. Hartley, “Subexpression sharing in filters using canonic signed digit multipliers,” IEEE Trans. Circuits Syst. II, vol. 43, no. 10, pp. 677–688, Oct. 1996.

    Article  Google Scholar 

  21. IEEE 754-2008 Standard for Floating-Point Arithmetic

    Google Scholar 

  22. K. Johansson, O. Gustafsson, and L. Wanhammar, “Power estimation for ripple-carry adders with correlated input data,” in Proc. Int. Workshop Power Timing Modeling Optimization Simulation, 2004.

    Google Scholar 

  23. S. Knowles, “A family of adders,” in Proc. Symp. Comput. Arithmetic, 1990, pp. 30–34.

    Google Scholar 

  24. P. Kornerup and D. W. Matula, Finite Precision Number Systems and Arithmetic, Cambridge University Press, 2010.

    Google Scholar 

  25. P. M. Kogge and H. S. Stone, “A parallel algorithm for the efficient solution of a general class of recurrence equations,” IEEE Trans. Comput., vol. 22, pp. 786–793, 1973.

    Article  MathSciNet  MATH  Google Scholar 

  26. I. Koren, Computer Arithmetic Algorithms, 2nd edition, A. K. Peters, Natick, MA, 2002.

    MATH  Google Scholar 

  27. R. E. Ladner and M. J. Fischer, “Parallel prefix computation,” J. ACM, vol 27, pp. 831–838. Oct. 1980.

    Google Scholar 

  28. J. Liang and T. D. Tran, “Fast multiplierless approximations of the DCT with the lifting scheme,” IEEE Trans. Signal Processing, vol. 49, no. 12, pp. 3032–3044, Dec. 2001.

    Article  Google Scholar 

  29. Y.-C. Lim, “Single-precision multiplier with reduced circuit complexity for signal processing applications,” IEEE Trans. Comput., vol. 41, no. 10, pp. 1333–1336, Oct. 1992.

    Article  Google Scholar 

  30. Y.-C. Lim, R. Yang, D. Li, and J. Song, “Signed power-of-two term allocation scheme for the design of digital filters,” IEEE Trans. Circuits Syst. II, vol. 46, no. 5, pp. 577–584, May 1999.

    Article  Google Scholar 

  31. B. Liu, “Effect of finite word length on the accuracy of digital filters – a review,” IEEE Trans. Circuit Theory, vol. 18, pp. 670–677, Nov. 1971.

    Article  Google Scholar 

  32. B. Liu and T. Kaneko, “Error analysis of digital filters realized with floating-point arithmetic,” Proc. IEEE, vol. 57, pp. 1735–1747, Oct. 1969.

    Article  Google Scholar 

  33. O. L. MacSorley, “High-speed arithmetic in binary computers,” Proc. IRE, vol. 49, no. 1, pp. 67–91, Jan. 1961.

    Article  MathSciNet  Google Scholar 

  34. P. K. Meher, J. Valls, T.-B. Juang, K. Sridharan, and K. Maharatna, “50 years of CORDIC: Algorithms, architectures and applications,” IEEE Trans. Circuits Syst. I, vol. 56, no. 9, pp. 1893–1907, Sept. 2009.

    Google Scholar 

  35. Z.-J. Mou and F. Jutand, “’Overturned-Stairs’ adder trees and multiplier design,” IEEE Trans. Comput., vol. 41, no. 8, pp. 940–948, Aug. 1992.

    Google Scholar 

  36. J.-M. Muller, Elementary Functions: Algorithms and Implementation, 2nd Edition, Birkhäuser Boston, 2006.

    Google Scholar 

  37. J.-M. Muller, N. Brisebarre, F. de Dinechin, C.-P. Jeannerod, V. Lefévre, G. Melquiond, N. Revol, D. Stehlé, and S. Torres, Handbook of Floating-Point Arithmetic, Birkhäuser Boston, 2010.

    Google Scholar 

  38. V. G. Oklobdzija, D. Villeger, and S. S. Liu, “A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach,” IEEE Trans. Comput., vol. 45, no. 3, Mar. 1996.

    Google Scholar 

  39. A. Omondi and B. Premkumar, Residue Number Systems: Theory and Implementation, Imperial College Press, 2007.

    Google Scholar 

  40. S. T. Oskuii, P. G. Kjeldsberg, and O. Gustafsson, “A method for power optimized partial product reduction in parallel multipliers,” in Proc. IEEE Norchip Conf., 2007.

    Google Scholar 

  41. B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs, 2nd edition, Oxford University Press, New York, 2010.

    Google Scholar 

  42. N. Petra, D. De Caro, V. Garofalo, E. Napoli, and A. G. M. Strollo, “Truncated binary multipliers with variable correction and minimum mean square error,” IEEE Trans. Circuits Syst. I, 2010.

    Google Scholar 

  43. M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, “Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination,” IEEE Trans. Computer-Aided Design, vol. 15, no. 2, pp. 151–165, Feb. 1996.

    Article  Google Scholar 

  44. M. Püschel, J. M. F. Moura, J. Johnson, D. Padua, M. Veloso, B. Singer, J. Xiong, F. Franchetti, A. Gacic, Y. Voronenko, K. Chen, R. W. Johnson, and N. Rizzolo, “SPIRAL: Code generation for DSP transforms,” Proc. IEEE, vol. 93, no. 2, pp. 232–275, Feb. 2005.

    Article  Google Scholar 

  45. B. D. Rao, “Floating point arithmetic and digital filters,” IEEE Trans. Signal Processing, vol. 40, no. 1, pp. 85–95, Jan. 1992.

    Article  Google Scholar 

  46. H. Samueli and A. N. Willson Jr., “Nonperiodic forced overflow oscillations in digital filters,” IEEE Trans. Circuits Syst., vol. 30, no. 10, pp. 709–722, Oct. 1983.

    Article  MathSciNet  MATH  Google Scholar 

  47. M. J. Schulte and J. E. Stine, “Approximating elementary functions with symmetric bipartite tables,” IEEE Trans. Comput., no. 8, vol. 48, pp. 842–847, Aug. 1999.

    Google Scholar 

  48. P. F. Stelling and V. G. Oklobdzija, “Design strategies for optimal hybrid final adders in a parallel multiplier,” J. VLSI Signal Processing, vol. 14, no. 3, pp. 321–331, Dec. 1996.

    Article  Google Scholar 

  49. D. Timmerman, H. Hahn, B. J. Hosticka, and B. Rix, “A new addition scheme and fast scaling factor compensation methods for CORDIC algorithms,” Integration, the VLSI Journal, vol. 11, pp. 85–100, Nov. 1991.

    Google Scholar 

  50. J. E. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Elec. Comput., vol. 8, pp. 330–334, 1959.

    Article  Google Scholar 

  51. J. E. Volder, “The birth of CORDIC,” J. VLSI Signal Processing, vol. 25, 2000.

    Google Scholar 

  52. Y. Voronenko and M. Püschel, “Multiplierless multiple constant multiplication,” ACM Trans. Algorithms vol. 3, no. 2, May 2007.

    Google Scholar 

  53. C. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. Electron. Comput., vol. 13, no. 1, pp. 14–17, Feb. 1964.

    Article  MATH  Google Scholar 

  54. J. S. Walther, “A unified algorithm for elementary functions,” Spring Joint Computer Conf. Proc., vol. 38, pp. 379–385, 1971.

    Google Scholar 

  55. J. S. Walther, “The story of unified CORDIC,” J. VLSI Signal Processing, vol. 25, 2000.

    Google Scholar 

  56. L. Wanhammar, DSP Integrated Circuits, Academic Press, 1999.

    Google Scholar 

  57. B. Zeng and Y. Neuvo, “Analysis of floating point roundoff errors using dummy multiplier coefficient sensitivities,” IEEE Trans. Circuits Syst., vol. 38, no. 6, pp. 590–601, June 1991.

    Article  Google Scholar 

  58. R. Zimmermann, Binary adder architectures for cell-based VLSI and their synthesis, Ph.D. Thesis, Swiss Federal Institute of Technology (ETH), Zurich, Hartung-Gorre Verlag, 1998.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Linköping University, SE-581 83, Linköping, Sweden

    Oscar Gustafsson & Lars Wanhammar

Authors
  1. Oscar Gustafsson
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Lars Wanhammar
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Oscar Gustafsson .

Editor information

Editors and Affiliations

  1. , Dept. of Electrical and, University of Maryland, A. V. Williams Bldg. 2311, College Park, 20742, Maryland, USA

    Shuvra S. Bhattacharyya

  2. Leiden Inst. Advanced Computer Science, Leiden Embedded Research Center, Leiden University, Niels Bohrweg 1, Leiden, 2333 CA, Netherlands

    Ed F. Deprettere

  3. Software for Systems on Silicon, RWTH Aachen University, Templergraben 55, Aachen, 52056, Germany

    Rainer Leupers

  4. , Department of Pervasive Computing, Tampere University of Technology, Korkeakoulunkatu 1, Tampere, 33720, Finland

    Jarmo Takala

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Gustafsson, O., Wanhammar, L. (2013). Arithmetic. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6859-2_19

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-6859-2_19

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-6858-5

  • Online ISBN: 978-1-4614-6859-2

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation