Throughout this book, the most relevant results and main conclusions have been summarized in the concluding discussion of each chapter. In this final chapter, the most significant contributions will be reported to give a general overview of the work.

First, the fulfillment of the main objectives presented in Sect. 1.3 will be verified, leading to the corresponding conclusions. Then, further research directions will be pointed out. Among these are issues not considered in this book, as well as the more in-depth development of some of those already accomplished. These proposed investigations could well be used in future works as an extension to complete the work presented here.

5.1 General Conclusions

The increased emergence of WSN technology has raised the use of the so-called smart sensors to monitor different physical or chemical parameters. These sensors include in the same chip, besides the sensing element, the conditioning circuit that provides a digital signal to be read by a digital port of a microcontroller. Nevertheless, to achieve a low-cost solution, the use of low-cost analog sensors, followed by an only electronic interface integrated in CMOS technology is becoming the preferable choice.

These interfaces have to be low-power and reconfigurable to adapt different types of sensors. They usually consist of a programmable voltage adapter that adjusts the gain and offset of the sensor signals to fit a common output range, and an analog-to-digital converter that digitizes the signal that will be driven to the microcontroller. For digitalization, quasi-digital converters are becoming widely used due to their time-measurement capabilities. Under this premise, this book focused on the design of CMOS voltage-to-frequency converters for this task because of their overwhelming advantages in terms of simplicity or noise immunity. The essential challenges to cope with are the power consumption, for its use in battery-operated interfaces, and the input range, that must be rail-to-rail for an optimum digitalization.

From an exhaustive review of the most frequently used types of VFCs, multivibrator VFC has been selected for a CMOS low-voltage single-supply implementation attaining low-power operation. This type of VFC usually consists of a voltage-to-current converter, a bidirectional current integrator, and a control circuit.

Several V-I converters have been studied, starting from the classical OTA-NMOS-grounded resistor structure, which achieves high linearity, but exhibits rather limited input range. Though significant swing extension is achieved using an OTA/common source amplifier V-I scheme, this converter still presents a limited input range. Therefore, three compact and simple novel CMOS V-I converters have been presented. These 1.2 V–0.18 μm CMOS converters attain rail-to-rail operation, require low power (below 80 μW), are temperature compensated over a (−40, +120 °C) range and achieve high linearity (maximum transconductance deviation below 30 % over all the temperature range) with an active area below 0.0145 μm2, showing very competitive performances when compared with the state-of-the-art rail-to-rail V-I converters, being not only suitable for use in VFCs, but also in other applications.

Two proposals for bidirectional current integrators with grounded capacitor compatible with low-voltage low-power design have been presented. The first one is a conventional approach and the second one is less power demanding, allowing a better current copy. The possibility to add programmability and an offset frequency to the VFC by introducing simple modifications in the bidirectional current integrator has been shown. Programmability has been achieved by means of including several digitally controlled current mirrors with different scaling factors, whereas the offset frequency is attained by introducing an offset current at this point, which is added to the scaled current that flows through the current mirrors. With these two features a versatile VFC can be obtained.

The control circuit, responsible for providing the switching signals required by the bidirectional current integrator as well as the VFC output signal, is based on a voltage-window comparator (VWC), consisting of two differential pairs followed by inverters and a \( \overline{\mathrm{ RS}} \) flipflop, instead of a Schmitt trigger comparator, to attain process independent comparison limits and providing a relatively fast response. A power consumption reduction technique is performed, making the comparators in the VWC work alternately. In this block a compromise between power consumption and introduced delay has to be taken into account.

Several proposals to generate the comparison limits of the VWC and the bias current have also been introduced, from the simplest solutions to complete temperature and supply voltage independent solutions. In addition, whenever possible, an enable terminal has been included to set the VFC into a sleep-mode when no conversion is required, thus achieving extreme reduction in the power consumption of the system.

Subsequently, four different VFCs implemented in the 0.18-μm CMOS technology provided by UMC have been developed with the previously presented building blocks.

The first proposal (VFC1) is based on an enhanced V-I converter followed by the conventional bidirectional current integrator, and includes temperature compensation, digitally programmable output frequency range, and a sleep-mode terminal to power down the device when it is inactive. The measured results of this low-voltage (V DD = 1.8 V) low-power (0.4 mW in full operation and 35 nW in sleep-mode) VFC confirm an input range of [0.1, 1.6 V] and digitally selectable sensitivities of 312.5, 625 and 937.5 kHz/V with a linearity error of 11 bits over a temperature variation of (−40, +120 °C).

The second proposal (VFC2) is based on a rail-to-rail feedback voltage attenuation V-I converter, followed by the low-power bidirectional current integrator, and includes temperature compensation and an offset frequency. The measured results of this low-voltage (V DD = 1.2 V) low-power (below 70 μW) VFC confirm a full input range and an output frequency range of [0.1, 1.0 MHz] with a linearity error of 12 bits over a temperature variation of (−40, +120 °C).

Finally, two rail-to-rail temperature-compensated differential VFCs (VFC3 and VFC4) based on the rail-to-rail feedback voltage attenuation V-I converter have been proposed. VFC3 is a low-voltage (V DD = 1.2 V) low-power (65 μW) dVFC with an output range of [0.0 – 0.9 MHz], a linearity error of 13 bits over temperature variation of (−40, +120 °C) and supply voltage variation of ±30 %. VFC4 is a low-voltage (V DD = 1.2 V) low-power (75 μW) dVFC that can operate either with single or differential input signals. Simulation results over a (−40, +120 °C) temperature range and supply voltage variations of ±30 % show an output frequency range of [0.0 – 0.9 MHz] with a linearity error of 13 bits in single mode and a linearity error of 14 bits in differential mode.

The general specifications imposed for the VFCs presented in this book were a maximum voltage supply of V DD = 1.8 V, a power consumption below 1 mW, and an output frequency below 2 MHz with temperature and supply voltage independent sensitivity and a maximum linearity error of 0.1 % (10 bits). These requirements have been progressively achieved and, on the whole, the proposed VFCs are more than competitive with those already presented in the literature. They exhibit a larger operating range, coming to obtain rail-to-rail operation, while keeping fairly good performances in terms of sensitivity, linearity and power consumption. Consequently, VFCs are a good alternative for future multisensory read out interfaces to be used in battery-operated systems.

5.2 Further Research Directions

All the proposed VFCs use simple differential pairs followed by inverters as comparators to implement the VWC control circuit, to have a fast response. However, to keep power consumption bounded, the differential pairs biasing current is bounded, causing an increase in the delay introduced to the VFC, thus increasing the relative and sensitivity errors in the system. Therefore, the design of new comparators that have a fast response as well as low-power consumption offers a new research line that could be very advantageous for portable applications.

The β-multiplier bias circuit explained in Sect. 3.4 and the generation circuit of the VWC comparison limits explained in Sect. 3.3, with two resistors driven by the bias current, provide temperature and supply voltage independent bias current and V H and V L, respectively. Though these solutions have been validated through the operation of VFC3, and VFC4, the research in the design of bias circuits and voltage references introduces a new field of study that should be developed further to obtain optimum LV-LP solutions, and has been set aside for future investigation lines. Another open issue in the field of biasing is the implementation of an on-chip voltage regulator that feeds the complete system, thus having full V DD insensitivity. This voltage regulator should include an easy enable that drives the system into a sleep-mode, to achieve a complete on-chip solution that includes power management.

Finally, integration of the programmable voltage adapter in the same chip of the VFC is desirable to have a complete electronic multisensor interface.

Thus, the future work clearly outlined will aid in the completion of the study carried out in this book as well as help to explore new research direction.