CMOS Reliability Overview

  • Elie Maricau
  • Georges Gielen
Part of the Analog Circuits and Signal Processing book series (ACSP)


For over four decades, scientists have been scaling devices to increasingly smaller feature sizes (Lewyn et al. 2009; International technology roadmap for semiconductors 2011). This trend is driven by a seemingly unending demand for ever-better performance and by fierce global competition. The steady CMOS technology downscaling is needed to meet requirements on speed, complexity, circuit density, power consumption and ultimately cost required by many advanced applications. However, going to these ultra-scaled CMOS devices also brings some drawbacks.


CMOS Technology Gate Dielectric Gate Oxide International Electrotechnical Commission Negative Bias Temperature Instability 
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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.ESAT-MICASKU LeuvenHeverleeBelgium

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