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Analysis and Mitigation of TSV-Induced Substrate Noise

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Designing TSVs for 3D Integrated Circuits

Part of the book series: SpringerBriefs in Electrical and Computer Engineering ((BRIEFSELECTRIC))

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Abstract

TSVs are a major source of substrate noise that threatens the performance of neighboring devices. In addition, TSV noise increases leakage current, which increases static power consumption and can erroneously switch transistors off or on [91]. A “keep out” zone, specified through layout rules, is thus required to shield devices from neighboring TSVs.

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References

  1. Ansoft - Q3D Extractor. http://www.ansoft.com/products/si/q3d_extractor/, http://www.ansoft.com/products/si/q3d_extractor/

  2. MITLL Low-Power FDSOI CMOS Process. http://www.ece.umd.edu/~dilli/research/layout/MITLL_3D_2006/3D_PDK2.3/doc/ApplicationNotes2006-1.pdf, http://www.ece.umd.edu/~dilli/research/layout/MITLL_3D_2006/3D_PDK2.3/doc/ApplicationNotes2006-1.pdf

  3. Predictive technology model (PTM). http://www.eas.asu.edu/˜ptm/

  4. Redistributed Chip Packaging (RCP) Technology. http://www.freescale.com/webapp/sps/site/overview.jsp?code=ASIC_LV3_PACKAGING_RCP. http://www.freescale.com/webapp/sps/site/overview.jsp?code=ASIC_LV3_PACKAGING_RCP

  5. (2009) International Technology Roadmap for Semiconductors. http://wwwitrsnet/Links/2009ITRS/Home2009htm http://www.itrs.net/

  6. Afzali-Kusha A, Nagata M, Verghese N, Allstot D (2006) Substrate noise coupling in SoC design: modeling, avoidance, and validation. Proc IEEE 94(12):2109–2138

    Google Scholar 

  7. Alam SM, Jones RE, Rauf S, Chatterjee R (2007) Inter-Strata connection characteristics and signal transmission in three-dimensional (3D) integration technology. In: 8th international symposium on quality electronic design, pp 580–585

    Google Scholar 

  8. Andry P, Tsang C, Sprogis E, Patel C, Wright S, Webb B, Buchwalter L, Manzer D, Horton R, Polastre R, Knickerbocker J (2006) A CMOS-compatible process for fabricating electrical through-vias in silicon. In: Electronic components and technology conference, pp 831–837

    Google Scholar 

  9. Andry PS, Tsang CK, Webb BC, Sprogis EJ, Wright SL, Dang B, Manzer DG (2008) Fabrication and characterization of robust through-silicon vias for silicon-carrier applications. IBM J Res Develop 52(6):571–581

    Google Scholar 

  10. Bakir M, King C, Sekar D, Thacker H, Dang B, Huang G, Naeemi A, Meindl J (2008) 3D Heterogeneous integrated systems: liquid cooling, power delivery, and implementation. In: IEEE custom integrated circuits conference, pp 663–70

    Google Scholar 

  11. Bamal M, List S, Stucchi M, Verhulst A, Hove MV, Cartuyvels R, Beyer G, Maex K (2006) Performance comparison of interconnect technology and architecture options for deep submicron technology nodes. In: International interconnect technology conference, pp 202–204

    Google Scholar 

  12. Banerjee K, Srivastava N (2006) Are carbon nanotbues the future of VLSI interconnects? In: 43rd IEEE/ACM annual conference on design automation, pp 809–814

    Google Scholar 

  13. Banerjee K, Im S, Srivastava N (2005) Interconnect modeling and analysis in the nanometer era: Cu and beyond. In: 22nd advanced metallization conference

    Google Scholar 

  14. Banerjee K, Li H, Srivastava N (2008) Current status and future perspectives of carbon nanotube interconnects. In: 8th IEEE conference on nanotechnology, pp 432–436

    Google Scholar 

  15. Baughman RH, Zakhidov AA, De Heer WA (2002) Carbon nanotubes – the route toward applications. Science 297(5582):787–792

    Google Scholar 

  16. Beattie M, Pileggi L (2001) Inductance 101: modeling and extraction. In: 38th design automation conference, pp 323–328

    Google Scholar 

  17. Beica R, Siblerud P, Sharbono C, Bernt M (2008) Advanced metallization for 3D integration. In: 10th electronics packaging technology conference, pp 212–218

    Google Scholar 

  18. Beyne E (2008) Solving technical and economical barriers to the adoption of Through-Si-Via 3D integration technologies. In: 10th electronics packaging technology conference, pp 29–34

    Google Scholar 

  19. Bhattacharya U, Wang Y, Hamzaoglu F, Ng Y, Wei L, Chen Z, Rohlman J, Young I, Zhang K (2008) 45nm SRAM technology development and technology lead vehicle. Intel Tech J 12(02)

    Google Scholar 

  20. Borkar S (2009) Design perspectives on 22nm CMOS and beyond. In: 46th ACM/IEEE design automation conference, pp 93–94

    Google Scholar 

  21. Brooks D, Tiwari V, Martonosi M (2000) Wattch: a framework for architectural-level power analysis and optimizations. In: 27th international symposium on computer architecture, pp 83–94

    Google Scholar 

  22. Burke P (2002) Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes. IEEE Trans Nanotechnol 1(3):129–144

    Google Scholar 

  23. Burns J, Aull B, Chen C, Chen C, Keast C, Knecht J, Suntharalingam V, Warner K, Wyatt P, Yost D (2006) A wafer-scale 3-D circuit integration technology. IEEE Trans Electron Dev 53(10):2507–2516

    Google Scholar 

  24. Cantoro M, Hofmann S, Pisana S, Scardaci V, Parvez A, Ducati C, Ferrari A, Blackburn A, Wang K, Robertson J (2006) Catalytic chemical vapor deposition of single-wall carbon nanotubes at low temperatures. Nano Lett 6(6):1107–1112

    Google Scholar 

  25. Cao A, Baskaran R, Frederick M, Turner K, Ajayan P, Ramanath G (2003) Direction-selective and length-tunable in-plane growth of carbon nanotubes. Adv Mater 15(13):1105–1109

    Google Scholar 

  26. Chang M (2007) Foundry future: challenges in the 21st century. In: IEEE international solid-state circuits conference, pp 18–23

    Google Scholar 

  27. Chen D, Chiou W, Chen M, Wang T, Ching K, Tu H, Wu W, Yu C, Yang K, Chang H, Tseng M, Hsiao C, Lu Y, Hu H, Lin Y, Hsu C, Shue W, Yu C (2009) Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking. In: IEEE international electron devices meeting, pp 1–4

    Google Scholar 

  28. Chen T, Chen CC (2001) Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods. In: IEEE/ACM design automation conference, pp 559–562

    Google Scholar 

  29. Cheung C, Kurtz A, Park H, Lieber C (2002) Diameter-controlled synthesis of carbon nanotubes. J Phys Chem B 106(10):2429–2433

    Google Scholar 

  30. Cho J, Shim J, Song E, Pak JS, Lee J, Lee H, Park K, Kim J (2009) Active circuit to through silicon via (TSV) noise coupling. In: IEEE 18th conference on electrical performance of electronic packaging and systems, pp 97–100

    Google Scholar 

  31. Clement F (2001) Substrate noise coupling analysis in mixed-signal ICs. Presentation from the workshop on substrate-noise coupling in mixed-signal ICs, IMEC, Leuven, Belgium, September 56

    Google Scholar 

  32. Cong J, Zhang Y (2005) Thermal-driven multilevel routing for 3-D ICs. In: Asia and South Pacific design automation conference, pp 121–126

    Google Scholar 

  33. Datta S (2005) Quantum transport: atom to transistor, 2nd edn. Cambridge University Press, Cambridge

    Google Scholar 

  34. Davis W, Wilson J, Mick S, Xu J, Hua H, Mineo C, Sule A, Steer M, Franzon P (2005) Demystifying 3D ICs: The Pros and Cons of going vertical. IEEE Des Test Comput 22(6):498–510

    Google Scholar 

  35. Denda S (2007) Process examination of through silicon via technologies. In: 6th international conference on polymers and adhesives in microelectronics and photonics, pp 149–152

    Google Scholar 

  36. Duesberg GS, Graham AP, Kreupl F, Liebau M, Seidel R, Unger E, Hoenlein W (2004) Ways towards the scaleable integration of carbon nanotubes into silicon based technology. Diam Relat Mater 13(2):354–361

    Google Scholar 

  37. Early J (1960) Speed, power and component density in multielement high-speed logic systems. In: IEEE international solid-state circuits conference, vol III, pp 78–79

    Google Scholar 

  38. Garrou P, Bower C, Ramm P (2008) Handbook of 3D integration: technology and applications of 3D integrated circuits. Wiley-VCH, Weinheim

    Google Scholar 

  39. Goering R (2009) A qualcomm perspective on 3D ICs. http://wwwcadencecom/community/blogs/ii/archive/2009/04/20/a-qualcomm-perspective-on-3d-icsaspx

  40. Golshani1 N, Derakhshandeh1 J, Ishihara1 R, Beenakker C, Robertson2 M, Morrison T (2010) Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon. In: IEEE international conference on 3D system integration, pp 1–7

    Google Scholar 

  41. Goplen B, Sapatnekar S (2006) Placement of thermal vias in 3-D ICs using various thermal objectives. IEEE Trans Computer Aided Des Integrated Circ Syst 25(4):692–709

    Google Scholar 

  42. Gupta M, Oatley J, Joseph R, Wei G, Brooks D (2007) Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. In: Design, automation test in Europe, pp 1–6

    Google Scholar 

  43. Haruehanroengra S, Wang W (2007) Analyzing conductance of mixed carbon-nanotube bundles for interconnect applications. IEEE Electron Dev Lett 28(8):756–759

    Google Scholar 

  44. Ho SW, Rao VS, Khan QKN, Yoon SU, Kripesh V (2006) Development of coaxial shield via in silicon carrier for high frequency application. In: 8th electronics packaging technology conference, pp 825–830

    Google Scholar 

  45. Ho SW, Yoon SW, Zhou Q, Pasad K, Kripesh V, Lau J (2008) High RF performance TSV silicon carrier for high frequency application. In: 58th electronic components and technology conference, pp 1946–1952

    Google Scholar 

  46. Huang G, Bakir M, Naeemi A, Chen H, Meindl J (2007) Power delivery for 3D chip stacks: physical modeling and design implication. In: IEEE electrical performance of electronic packaging, pp 205–208

    Google Scholar 

  47. Ishikuro H, Miura N, Kuroda T (2007) Wideband inductive-coupling interface for high-performance portable system. In: IEEE custom integrated circuits conference, pp 13–20

    Google Scholar 

  48. Jain P, Kim T, Keane J, Kim CH (2008) A multi-story power delivery technique for 3D integrated circuits. In: 13th international symposium on low power electronics and design, pp 57–62

    Google Scholar 

  49. Jang DM, Ryu C, Lee KY, Cho BH, Kim J, Oh TS, Lee WJ, Yu J (2007) Development and evaluation of 3-D SiP with vertically interconnected through silicon vias (TSV). In: Electronic components and technology conference, pp 847–852

    Google Scholar 

  50. Joyner J, Venkatesan R, Zarkesh-Ha P, Davis J, Meindl J (2001) Impact of three-dimensional architectures on interconnects in gigascale integration. IEEE Trans Very Large Scale Integ (VLSI) Syst 9(6):922–928

    Google Scholar 

  51. Keigler A, O’Donnell K, Liu Z, Wu B, Trezza J (2007) Enabling 3-D design. Semicond Int 30(9):36–44

    Google Scholar 

  52. Khan NH, Alam SM, Hassoun S (2009) Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies, very large scale integration (VLSI) systems, IEEE Transactions on, vol.19, no.4, pp.647–658, April 2011

    Google Scholar 

  53. Khan N, Alam S, Hassoun S (2009) Through-silicon via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. In: IEEE international conference on 3D system integration, pp 1–7

    Google Scholar 

  54. Kikuchi H, Yamada Y, Ali AM, Liang J, Fukushima T, Tanaka T, Koyanagi M (2008) Tungsten through-silicon via technology for three-dimensional LSIs. Jpn J Appl Phys 47:2801–2805

    Google Scholar 

  55. Kim B, Sharbono C, Ritzdorf T, Schmauch D (2006) Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking. In: 56th electronic components and technology conference, pp 838–843

    Google Scholar 

  56. King C, Sekar D, Bakir M, Dang B, Pikarsky J, Meindl J (2008) 3D Stacking of chips with electrical and microfluidic I/O interconnects. In: Electronic components and technology conference, pp 1–7

    Google Scholar 

  57. Knickerbocker J, Patel C, Andry P, Tsang C, Buchwalter L, Sprogis E, Gan H, Horton R, Polastre R, Wright S, Cotte J (2006) 3-D silicon integration and silicon packaging technology using silicon through-vias. IEEE J Solid State Circ 41(8):1718–1725

    Google Scholar 

  58. Kreupl F, Graham AP, Liebau M, Duesberg GS, Seidel R, Unger E (2004) Carbon nanotubes for interconnect applications. In: International electron devices meeting, pp 683–686

    Google Scholar 

  59. Kuo WS, Wang M, Chen E, Lai JY, Wang YP (2008) Thermal investigations of 3D FCBGA packages with TSV technology. In: 3rd international microsystems, packaging, assembly circuits technology conference, pp 251–254

    Google Scholar 

  60. Kurita Y, Soejima K, Kikuchi K, Takahashi M, Tago M, Koike M, Shibuya K, Yamamichi S, Kawano M (2006) A novel “SMAFTI” package for inter-chip wide-band data transfer. In: 56th electronic components and technology conference, pp 289–297

    Google Scholar 

  61. Laviron C, Dunne B, Lapras V, Galbiati P, Henry D, Toia F, Moreau S, Anciant R, Brunet-Manquat C, Sillon N (2009) Via first approach optimisation for through silicon via applications. In: 59th electronic components and technology conference, pp 14–19

    Google Scholar 

  62. Lee Y, Goel R, Lim SK (2009) Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs. In: IEEE/ACM international conference on computer-aided design, pp 645–51

    Google Scholar 

  63. Lee Y, Yoon JK, Gang H, Bakir M, Joshi Y, Fedorov A, Sung KL (2009) Co-design of signal, power, and thermal distribution networks for 3D ICs. In: Design, automation and test in Europe, pp 610–615

    Google Scholar 

  64. Li H, Lu W, Li J, Bai X, Gu C (2005) Multichannel ballistic transport in multiwall carbon nanotubes. Phys Rev Lett 95(8):86,601–86,601

    Google Scholar 

  65. Loh GH (2008) 3D-stacked memory architectures for multi-core processors. In: 35th international symposium on computer architecture, pp 453–464

    Google Scholar 

  66. Loh GH, Xie Y, Black B (2007) Processor design in 3D die-stacking technologies. Micro IEEE 27(3):31–48

    Google Scholar 

  67. Loiseau A, Launois P, Petit P, Roche S, Salvetat J (2006) Understanding carbon nanotubes: from basics to applications. Springer, New York

    Google Scholar 

  68. Massoud Y, Nieuwoudt A (2006) Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits. ACM J Emerg Tech Comput Syst 2(3):155–196

    Google Scholar 

  69. McEuen P, Park JY (2004) Electron transport in single-walled carbon nanotubes. MRS Bull 29(4):272–275

    Google Scholar 

  70. Meindl J (2003) Beyond moore’s law: the interconnect era. Comput Sci Eng 5(1):20–24

    Google Scholar 

  71. Miao M, Jin Y, Liao H, Zhao L, Zhu Y, Sun X, Guo Y (2009) Research on deep RIE-based through-si-via micromachining for 3-D system-in-package integration. In: 4th IEEE international conference on nano/micro engineered and molecular systems, pp 90–93

    Google Scholar 

  72. Minz JR, Lim SK, Koh C (2005) 3D module placement for congestion and power noise reduction. In: Proceedings of the 15th ACM Great Lakes symposium on VLSI, pp 458–461

    Google Scholar 

  73. Mofrad MRT, Derakhshandeh J, Ishihara R, Baiano A, van der Cingel J, Beenakker K (2009) Stacking of single-grain thin-film transistors, Japanese journal of applied physics, vol. 48, p. 03B015-03B015-4, March 2009

    Google Scholar 

  74. Moore G (2003) No exponential is forever: but ”Forever” can be delayed! In: IEEE international solid-state circuits conference, pp 20–23

    Google Scholar 

  75. Moore GE (1965) Cramming more components onto integrated circuits. Electronics 38(8):114–117

    Google Scholar 

  76. Morrow P, Kobrinsky M, Ramanathan S, Park C, Harmes M, Ramachandrarao V, mog Park H, Kloster G, List S, Kim S (2005) Wafer-level 3D interconnects via Cu bonding. In: Advanced metallization conference, pp 125–30

    Google Scholar 

  77. Motoyoshi M (2009) Through-silicon via (TSV). Proc IEEE 97(1):43–48

    Google Scholar 

  78. Naeemi A, Meindl JD (2009) Carbon nanotube interconnects. Ann Rev Mater Res 39:255–275

    Google Scholar 

  79. Naeemi A, Huang G, Meindl JD (2007) Performance modeling for carbon nanotube interconnects in on-chip power distribution. In: Electronic components and technology conference, pp 420–428

    Google Scholar 

  80. Nagarajan R, Ebin L, Dayong L, Seng SC, Prasad K, Balasubramanian N (2006) Development of a novel deep silicon tapered via etch process for through-silicon interconnection in 3-D integrated systems. In: 56th electronic components and technology conference, pp 383–387

    Google Scholar 

  81. Nihei M, Kondo D, Kawabata A, Sato S, Shioya H, Sakaue M, Iwai T, Ohfuti M, Awano Y (2005) Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner shells. In: IEEE 2005 international interconnect technology conference, pp 234–236

    Google Scholar 

  82. Park JY, Rosenblatt S, Yaish Y, Sazonova V, Ustunel H, Braig S, Arias T, Brouwer P, McEuen P (2004) Electron-phonon scattering in metallic single-walled carbon nanotubes. Nano Lett 4(3):517–520

    Google Scholar 

  83. Patel CS (2006) Silicon carrier for computer systems. In: 43rd ACM/IEEE design automation conference, pp 857–862

    Google Scholar 

  84. Patti R (2006) Three-dimensional integrated circuits and the future of system-on-chip designs. Proc IEEE 94(6):1214–1224

    Google Scholar 

  85. der Plas GV, Limaye P, Mercha A, Oprins H, Torregiani C, Thijs S, Linten D, Stucchi M, Guruprasad K, Velenis D, Shinichi D, Cherman V, Vandevelde B, Simons V, Wolf ID, Labie R, Perry D, Bronckers S, Minas N, Cupac M, Ruythooren W, Olmen JV, Phommahaxay A, de Potter de ten Broeck M, Opdebeeck A, Rakowski M, Wachter BD, Dehan M, Nelis M, Agarwal R, Dehaene W, Travaly Y, Marchal P, Beyne E (2010) Design issues and considerations for low-cost 3D TSV IC technology. In: 2010 IEEE international solid-state circuits conference, pp 148–149

    Google Scholar 

  86. Pozder S, Lu J, Kwon Y, Zollner S, Yu J, McMahon J, Cale T, Yu K, Gutmann R (2004) Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform. In: IEEE international interconnect technology conference, pp 102–106

    Google Scholar 

  87. Rabaey JM, Chandrakasan AP, Nikoli B (2002) Digital integrated circuits: a design perspective. Prentice hall, New Jersey

    Google Scholar 

  88. Rahman A, Trezza J, New B, Trimberger S (2006) Die stacking technology for terabit chip-to-chip communications. In: IEEE custom integrated circuits conference, pp 587–590

    Google Scholar 

  89. Ramaswami S (2010) Process equipment readiness for through-silicon via technologies. Solid State Tech 53(8):16–17

    Google Scholar 

  90. Rousseau M, Rozeau O, Cibrario G, Le Carval G, Jaud M-A, Leduc P, Farcy A, Marty A (2008) Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology. In: IMAPS device packaging conference, Phoenix, AZ: United States

    Google Scholar 

  91. Rousseau M, Jaud M, Leduc P, Farcy A, Marty A (2009) Impact of substrate coupling induced by 3D-IC architecture on advanced CMOS technology. In: microelectronics and packaging conference, pp 1–5

    Google Scholar 

  92. Schrom G, Liu D, Pichler C, Svensson C, Selberherr S (1994) Analysis of ultra-low-power CMOS with process and device simulation. In: 24th European solid state device research conference, pp 679–682

    Google Scholar 

  93. Schulz M (1999) The End of the Road for Silicon. Nature 399(6738):729–730

    Google Scholar 

  94. Selvanayagam C, Lau J, Zhang X, Seah S, Vaidyanathan K, Chai T (2009) Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps. IEEE Trans Adv Packag 32(4):720–728

    Google Scholar 

  95. Selvanayagam C, Zhang X, Rajoo R, Pinjala D (2010) Modelling stress in silicon with TSVs and its effect on mobility. In: 11th electronics packaging technology conference, pp 612–618

    Google Scholar 

  96. Singer P (2008) Through-silicon vias: ready for volume manufacturing? Semicond Int 31(3):22–26

    Google Scholar 

  97. Sparks TG, Alam SM, Chatterjee R, Rauf S (2006) Method of forming a through-substrate via. U.S. patent appl. 20080113505

    Google Scholar 

  98. Srivastava N, Banerjee K (2005) Performance analysis of carbon nanotube interconnects for VLSI applications. In: International conference on computer aided design, pp 383–390

    Google Scholar 

  99. Srivastava N, Joshi R, Banerjee K (2005) Carbon nanotube interconnects: implications for performance, power dissipation and thermal management. In: International electron devices meeting, pp 249–252

    Google Scholar 

  100. Stahl H, Appenzeller J, Martel R, Avouris P, Lengeler B (2000) Intertube coupling in ropes of single-wall carbon nanotubes. Phys Rev Lett 85(24):5186–5189

    Google Scholar 

  101. Sun X, Ji M, Ma S, Zhu Y, Kang W, Miao M, Jin Y (2010) Electrical characterization of sidewall insulation layer of TSV. In: 11th international conference on electronic packaging technology & high density packaging, pp 77–80

    Google Scholar 

  102. Tang Z (2010) Efficient design practices for thermal management of a TSV based 3D IC system. In: 19th international symposium on physical design, pp 59–59

    Google Scholar 

  103. Tarkiainen R, Ahlskog M, Penttilä J, Roschier L, Hakonen P, Paalanen M, Sonin E (2001) Multiwalled carbon nanotube: luttinger versus fermi liquid. Phys Rev B 64(19):195,412–195,415

    Google Scholar 

  104. Tezcan D, Pham N, Majeed B, Moor PD, Ruythooren W, Baert K (2007) Sloped through wafer vias for 3D wafer level packaging. In: 57th electronic components and technology conference, pp 643–647

    Google Scholar 

  105. Thompson S, Chau R, Ghani T, Mistry K, Tyagi S, Bohr M (2005) In search of forever, continued transistor scaling one new material at a time. IEEE Trans Semicond Manuf 18(1):26–36

    Google Scholar 

  106. Topol A, Tulipe DL, Shi L, Alam S, Frank D, Steen S, Vichiconti J, Posillico D, Cobb M, Medd S, Patel J, Goma S, DiMilia D, Robson M, Duch E, Farinelli M, Wang C, Conti R, Canaperi D, Deligianni L, Kumar A, Kwietniak K, D’Emic C, Ott J, Young A, Guarini K, Ieong M (2005) Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs). In: IEEE international electron devices meeting, pp 352–355

    Google Scholar 

  107. UKnickerbocker J, SAndry P, Dang B, RHorton R, JInterrante M, SPatel C, JPolastre R, Sakuma K, Sirdeshmukh R, JSprogis E, MSri-Jayantha S, MStephens A, WTopol A, KTsang C, CWebb B, LWright S (2008) Three-dimensional silicon integration. IBM J Res Dev 52(6):553–569

    Google Scholar 

  108. Ural A, Li Y, Dai H (2002) Electric-field-aligned growth of single-walled carbon nanotubes on surfaces. Appl Phys Lett 81:34–64

    Google Scholar 

  109. Vandevelde B, Okoro C, Gonzalez M, Swinnen B, Beyne E (2008) Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologies. In: International conference on thermal, mechanical and multi-physics simulation and experiments in microelectronics and micro-systems, pp 1–7

    Google Scholar 

  110. Vardaman J, Garrou P (2010) Global trends in 3D IC packaging. Adv Microelectron 37(3):6–8

    Google Scholar 

  111. Wang W, Haruehanroengra S, Shang L, Liu M (2007) Inductance of mixed carbon nanotube bundles. Micro Nano Lett 2(2):35–39

    Google Scholar 

  112. Wei B, Vajtai R, Ajayan P (2001) Reliability and current carrying capacity of carbon nanotubes. Appl Phys Lett 79(8):1172–1174

    Google Scholar 

  113. Wong E, Lim SK (2006) 3D Floorplanning with thermal vias. In: Design, automation and test in Europe, pp 878–883

    Google Scholar 

  114. Wu JH (2006) Through-substrate interconnects for 3-D integration and RF systems. PhD dissertation, Department of EECS, Massachusetts Institute of Technology

    Google Scholar 

  115. Wunderle B, Mrossko R, Wittler O, Kaulfersch E, Ramm P, Michel B, Reichl H (2007) Thermo-mechanical reliability of 3-D-integrated microstructures in stacked silicon. In: Materials research society symposium, vol 67, pp 970–974

    Google Scholar 

  116. Xie B, Shi XQ, Chung CH, Lee SWR (2010) Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular through-silicon-via (TSV) design. In: 60th electronic components and technology conference, pp 1166–1172

    Google Scholar 

  117. Xie Y, Cong J, Sapatnekar S (2009) Three dimensional integrated circuit design: EDA, design and microarchitectures. Springer, New York

    Google Scholar 

  118. Y SSMMAKAKDSHITMMOMA (2006) Novel approach to fabricating carbon nanotube via interconnects using size-controlled catalyst nanoparticles. In: 2006 international interconnect technology conference, pp 230–232

    Google Scholar 

  119. Yu H, Ho J, He L (2006) Simultaneous power and thermal integrity driven via stapling in 3D ICs. In: IEEE/ACM international conference on computer-aided design, pp 802–808

    Google Scholar 

  120. Yu H, Ho J, He L (2009) Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. ACM Trans Des Autom Electron Syst 14(3):1–31

    Google Scholar 

  121. Zhan Y, Zhang T, Sapatnekar SS (2007) Module assignment for pin-limited designs under the stacked-vdd paradigm. In: IEEE/ACM international conference on computer-aided design, pp 656–659

    Google Scholar 

  122. Zheng LX, O’Connell MJ, Doorn SK, Liao XZ, Zhao YH, Akhadov EA, Hoffbauer MA, Roop BJ, Jia QX, Dye RC, et al (2004) Ultralong single-wall carbon nanotubes. Nat Mater 3(10):673,676

    Google Scholar 

  123. Zhou P, Sridharan K, Sapatnekar S (2009) Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. In: Asia and South Pacific design automation conference, pp 179–184

    Google Scholar 

  124. Zhu L, Xu J, Xiu Y, Sun Y, Hess DW, Wong CP (2006) Growth and electrical characterization of high-aspect-ratio carbon nanotube arrays. Carbon 44(2):253–258

    Google Scholar 

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  1. Department of Computer Science, Tufts University, 161 College Ave, Medford, USA

    Nauman Khan & Soha Hassoun

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  1. Nauman Khan
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  2. Soha Hassoun
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Khan, N., Hassoun, S. (2013). Analysis and Mitigation of TSV-Induced Substrate Noise. In: Designing TSVs for 3D Integrated Circuits. SpringerBriefs in Electrical and Computer Engineering. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-5508-0_3

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  • DOI: https://doi.org/10.1007/978-1-4614-5508-0_3

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-5507-3

  • Online ISBN: 978-1-4614-5508-0

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