Abstract
This chapter describes the CoSy-based [1, 2] compilers developed in the context of the REFLECT project to support its aspect-oriented design-flow. In particular, these CoSy-based compilers are guided by LARA strategies and are responsible for generating code targeting traditional processors, as well as generating behavioral-RTL VHDL code [3] targeting hardware accelerators. Throughout this chapter, these compilers are referred collectively as reflectc, except when a specific compilation flow (with its specific name) is used. We also describe the compiler development extensions to support the REFLECT approach [4] and the weaving process controlled by LARA strategies [5–7] as described in Chap. 3.
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Notes
- 1.
CoSy (COmpiler SYstem) is a registered trademark of ACE Associated Computer Experts bv.
- 2.
Common CoSy Medium-level Intermediate Representation.
- 3.
The LARA specifications consist mainly of aspect definitions and strategies. These core components are responsible for controlling and guiding the REFLECT design-flow by specifying design patterns and non-functional requirements.
- 4.
In REFLECT, join points refer to a static context (source construct or location). In general, however, join points are commonly known as points in the program’s execution.
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Nobre, R. et al. (2013). Hardware/Software Compilation. In: Cardoso, J., Diniz, P., de Figueiredo Coutinho, J., Petrov, Z. (eds) Compilation and Synthesis for Embedded Reconfigurable Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4894-5_5
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