A 12-bit 800 MS/s Dual-Residue Pipeline ADC

  • Jan Mulder
  • Davide Vecchi
  • Frank M. L. van der Goes
  • Jan R. Westra
  • Emre Ayranci
  • Christopher M. Ward
  • Jiansong Wan
  • Klaas Bult
Chapter

Abstract

This paper presents the design of a pipeline analog-to-digital converter (ADC) based on the dual-residue principle. By applying this technique, the ADC becomes insensitive to the exact gain of the MDAC residue amplifiers. This allows these amplifiers to be designed with a relatively low open-loop gain and low bandwidth, which is favorable for the power consumption of the ADC. The offsets of the residue amplifiers, however, limit the accuracy of the ADC. Therefore, offset calibration is required for the ADC to achieve a high resolution.

A 12-bit 800 MS/s dual-residue ADC was designed and implemented in a standard 40 nm CMOS technology. The high sampling speed was obtained through four times interleaving. The ADC achieves a peak SNDR of 59 dB. It operates from a dual 1 V/2.5 V power supply and consumes 105 mW.

Keywords

Expense Settling Polysilicon MDAC 

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Jan Mulder
    • 1
  • Davide Vecchi
    • 1
  • Frank M. L. van der Goes
    • 1
  • Jan R. Westra
    • 1
  • Emre Ayranci
    • 2
  • Christopher M. Ward
    • 1
  • Jiansong Wan
    • 1
  • Klaas Bult
    • 1
  1. 1.Broadcom Netherlands B.V.BunnikThe Netherlands
  2. 2.Now with ClariPhy Communications Inc.CAUSA

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