The Spidergon STNoC

  • Konstantinos Tatas
  • Kostas Siozios
  • Dimitrios Soudris
  • Axel Jantsch


Spidergon STNoC is a state-of-the-art, low-cost on-chip interconnect that plays a vital role in enabling multiprocessor system-on-chip by providing structure, performance, and modularity. This chapter outlines topological and routing characteristics of the packet-switched Spidergon STNoC, focusing on its low diameter, vertex-symmetric, point-to-point chordal ring topology, and its low-cost, efficient deterministic, shortest-path routing algorithm. It also describes interesting design tools and discusses new Spidergon extensions toward fault tolerant routing.


Network Interface Design Flow Virtual Channel Hardware Description Language Output Queue 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    P. Abad, P. Prieto, L.G. Menezo, A. Colaso, V. Puente, J.A. Gregorio, “TOPAZ: An open source interconnection network simulator for chip multi-processing and supercomputers”, in Proc. Symp. Networks-on-Chip, 2012, pp. 99–106.Google Scholar
  2. 2.
    Amba Bus, Arm,
  3. 3.
    A. Andriahantenaina, H. Charlery, A. Greiner, L. Mortiez and C. Zeferino, “SPIN: a scalable, packet switched, on-chip micro-network”, in Proc. Design, Automation & Test in Europe Conf., 2003, pp. 70–73.Google Scholar
  4. 4.
  5. 5.
    L. Benini, G. De Micheli, Networks on Chips: A new SoC paradigm. IEEE Computer, vol. 35(1), 70–781 (2002)CrossRefGoogle Scholar
  6. 6.
    J.C. Bermond, F. Comellas, D.F. Hsu, Distributed loop computer networks: a survey. J. Parallel Distrib. Comput. 24(1), 2–10 (1995)CrossRefGoogle Scholar
  7. 7.
    N. Binkert, B.M. Beckmann, G. Black, S.K. Reinhardt et al., The GEM5 simulator. ACM SIGARCH Computer Architecture News 39(2), 1 (2011)CrossRefGoogle Scholar
  8. 8.
    M. Chaudhuri, M. Heinrich, Exploring virtual network selection algorithms in DSM cache coherence protocols. IEEE Transactions on Parallel and Distributed Systems 15(8), 699–712 (2004)CrossRefGoogle Scholar
  9. 9.
    M. Coppola, S. Curaba, M.D. Grammatikakis, R. Locatelli, G. Maruccia, F. Papariello, OCCN: a NoC modeling framework for design exploration. J. Systems Arch. 50(2–3), 129–163 (2004)CrossRefGoogle Scholar
  10. 10.
    M. Coppola, M. D. Grammatikakis, R. Locatelli, G. Maruccia, and L. Pieralisi, “Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC”, CRC Press, 2008.Google Scholar
  11. 11.
    W.J. Dally, “Virtual-channel flow control”, IEEE Trans. Parallel Distrib. Syst., C-2 (2), 1992, pp. 194–205.Google Scholar
  12. 12.
    W.J. Dally, “Performance analysis of k-ary n-cube interconnection networks”, IEEE Trans. Computers, C-39 (6), 1990, pp. 775–785.Google Scholar
  13. 13.
    W.J. Dally and H. Aoki, “Deadlock-free adaptive routing in multi-computer networks using virtual channels”, IEEE Trans. Parallel Distrib. Syst., C-4 (4), 1993, pp. 466–474Google Scholar
  14. 14.
    W.J. Dally and C. Seitz, “Deadlock free message routing in multiprocessor interconnection networks”, IEEE Trans. Computers, C-36 (5), 1987, pp. 547–553Google Scholar
  15. 15.
    W.J. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks”, In Proc. IEEE/ACM Design Automation Conf., 2001, pp. 684–689Google Scholar
  16. 16.
    J. Ding and L.N. Bhuyan, “Analysis of multi-queue buffer allocation schemes in multistage interconnection networks”, Tech. Rep. - 053/93, Dept. Comput. Sci., Texas A & M University, 1993Google Scholar
  17. 17.
    J. Duato, S. Yalamanchili and L. Ni, “Interconnection networks: an engineering approach”, Morgan Kaufmann, 2nd Edition, 2002Google Scholar
  18. 18.
    M. Forsell, A scalable high-performance computing solution for networks on chips. IEEE Micro 22(5), 46–55 (2002)CrossRefGoogle Scholar
  19. 19.
    N. Genko, D. Atienza, G. De Micheli, J. M. Mendias, R. Hermida, F. Catthoor, “A complete network-on-chip emulation framework”, in Proc. Design Automation and Test in, Europe, 2005Google Scholar
  20. 20.
    C. Glass, L. Ni, “The turn model for adaptive routing”, J. ACM, v. 41(5), 874–902 (1994)CrossRefGoogle Scholar
  21. 21.
    G. Guindani, C. Reinbrecht, T. Raupp, N. Calazans, F.G. Moraes, “NoC power estimation at the RTL abstraction level”, in Proc (Symp, VLSI, 2008)Google Scholar
  22. 22.
    K. Goossens, J. Dielissen, J. van Meerbergen, P. Poplavko et al., “Guaranteeing the quality of services in networks on chip”, Networks on Chip (Kluwer Academic Publishers, Eds. A. Jantsch and H. Tenhunen, 2003)Google Scholar
  23. 23.
    M.D. Grammatikakis, D.F. Hsu and M. Kraetzl, “Parallel System Interconnections and Communications”, CRC press, 2000Google Scholar
  24. 24.
    F.K. Hwang, A complementary survey on double-loop networks. Theor. Comput. Sci. 263(1–2), 211–229 (2001)CrossRefMATHGoogle Scholar
  25. 25.
    F.K. Hwang, “A survey on multi-loop networks”, Theor. Comput. Sci., Elsevier (North Holland), 299(1–3), 2003, pp. 107–121Google Scholar
  26. 26.
    “IBM on-chip CoreConnect bus”, Available from
  27. 27.
    Y. Ben-Itzhak, E. Zahavi, I. Cidon and A. Kolodny, “HNOCS: Modular open source simulator for heterogeneous NoCs”, in Proc. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2012Google Scholar
  28. 28.
    A. Jalabert, S. Murali, L. Benini, G. De Micheli, “xpipesCompiler: A tool for instantiating application specific Networks on Chip”, in Proc (Automation & Test in Europe Conf, Design, 2004)Google Scholar
  29. 29.
    A. Kahng, B. Li, L.-S. Peh and K. Samadi, “ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration”, in Proc. Design Automation and Test in, Europe, 2009Google Scholar
  30. 30.
    G. Karypis and V. Kumar, “Metis: a software package for partitioning unstructured graphs, meshes, and computing fill-reducing orderings of sparse matrices (v 3.0.3)”, Tech. Rep., University of Minnesota, Dept. Comp. Sci. and Army HPC Research Center, November 1997Google Scholar
  31. 31.
    F.T. Leighton, Introduction to Parallel Algorithms and Architectures (Academic Press, New York, 1992)MATHGoogle Scholar
  32. 32.
    Z. Lu, R. Thid, M. Millberg, E. Nilsson and A. Jantsch, “NNSE: Nostrum NoC simulation environment”, in Proc. Design Automation and Test in, Europe, 2005Google Scholar
  33. 33.
    Z. Lu, “A user introduction to NNSE: Nostrum NoC simulation environment”, 2005, pp. 1–12, available from
  34. 34.
    J.A. Lukes, Combinatorial solution to the partitioning of general graphs. IBM Journal of Research and Development 19, 170–180 (1975)MathSciNetCrossRefMATHGoogle Scholar
  35. 35.
    M.M.K. Martin, D.J. Sorin, B.M. Beckmann, M.R. Marty et al., Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. ACM SIGARCH Computer Architecture News 33(4), 99 (2005)CrossRefGoogle Scholar
  36. 36.
    B. McKay. Nauty users guide (v 1.5), Technical report, Australian National University, Dept. Comp. Sci., 2009. Available from bdm/nauty/nug.pdf
  37. 37.
    M. Millberg, E. Nilsson, R. Thid, A. Jantsch, “Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip”, in Proc (Automation & Test in Europe Conf, Design, 2004)Google Scholar
  38. 38.
    F. Moraes, N. Calazans, A. Mello, L. Moller, L. Ost, Hermes: an infrastructure for low area overhead packet-switching networks on chip. Integr. VLSI J. 38, 69–93 (2004)CrossRefGoogle Scholar
  39. 39.
  40. 40.
  41. 41.
    S.C. North. NEATO user’s guide, Tech. Report, AT &T Bell Laboratories, Murray Hill, NJ, USA, October 2004. Available from
  42. 42.
  43. 43.
    OMNET, available from
  44. 44.
    V.S. Pai, P. Ranganathan, S. Adve, RSIM: Rice Simulator for ILP Multiprocessors. ACM SIGARCH Computer Architecture News 25(5), 1 (1997)CrossRefGoogle Scholar
  45. 45.
    V. Puente, J.A. Gregorio and R. Beivide, “Sicosys: An integrated framework for studying interconnection network performance in multiprocessor systems”, in Proc. Euromicro Conf. on Parallel, Distributed, and Network-Based Processing, 2002Google Scholar
  46. 46.
    Y. R. Sun, S. Kumar and A. Jantsch, “Simulation and evaluation of a network on chip architecture using NS-2”, in Proc. IEEE NorChip Conf., 2002, pp. 6Google Scholar
  47. 47.
    J. Upadhyay, V. Varavithya, and P. Mohapatra, “Routing algorithms for torus networks”, Int. Conf. High Perf. Comput., 1995, pp. 743–748Google Scholar
  48. 48.
    M. Taylor, J. Kim, J. Miller, D. Wentzlaff, et al., “The Raw micro-processor: a computational fabric for software circuits and general-purpose programs”, IEEE Micro, 22 (2), 20002, pp. 25–35. Also available from,
  49. 49.
    D. Wang, N.E. Jerger, J.G. Steffan, “DART: A programmable architecture for NoC simulation on FPGAs”, in Proc (Symp, Networks-on-Chip, 2011)Google Scholar
  50. 50.
    H. Wang, X. Zhu, L.-S. Peh and S. Malik, “Orion: A power-performance simulator for interconnection networks”, in Proc. of MICRO 35, Istanbul, Turkey, November 2002Google Scholar
  51. 51.
    E.W. Weisstein, “Moore Graph”, refer to
  52. 52.
    P. Wolkotte, P. Holzenspies, and G. Smit, “Fast, accurate and detailed NoC simulations”, in Proc. Symp. on Networks-on-Chip, 2007Google Scholar
  53. 53.
  54. 54.
    C. Chevalier, F. Pellegrini, PT-Scotch. Parallel Computing 34(6–8), 318–331 (2008)MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Konstantinos Tatas
    • 1
  • Kostas Siozios
    • 2
  • Dimitrios Soudris
    • 2
  • Axel Jantsch
    • 3
  1. 1.Department of Computer Science and Engineering, School of Applied SciencesFrederick UniversityNicosiaCyprus
  2. 2.Department of Computer Science, School of Electrical and Computer EngineeringNational Technical University of AthensAthensGreece
  3. 3.Department of Electronic SystemsRoyal Institute of TechnologyKistaSweden

Personalised recommendations