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Designing 2D and 3D Network-on-Chip Architectures pp 97–126Cite as

Power and Thermal Effects and Management

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Abstract

As semiconductor processes scale to smaller and smaller feature sizes, manufacturing reliable digital designs is challenging how systems are traditionally designed. Specifically, the shrinking of transistor and wire size imposes that these components simultaneously are becoming more prone to complete, or parametric, failure at manufacturing time. Additionally, the derived systems are increasingly expensive to produce and less likely to function correctly for as long as intended. In order to address these challenges, the NoC-based systems have to be designed with reliability and fault tolerance features in mind. Toward this goal, a number of design techniques and methodologies are available that promise to provide sufficient fault coverage with controllable overhead in terms of hardware redundancy and performance (e.g., delay/power) degradation. This chapter studies the origin of faults in modern technologies and explains the classification to transient, intermittent, and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, School of Applied Sciences, Frederick University, Y. Frederickou Str., Pallouriotisa 7, Nicosia, 1036, Cyprus

    Konstantinos Tatas

  2. Department of Computer Science, School of Electrical and Computer Engineering, National Technical University of Athens, Heroon Polytechneiou, Zographou Campus 9, 157 80, Athens, Greece

    Kostas Siozios & Dimitrios Soudris

  3. Department of Electronic Systems, Royal Institute of Technology, ECS/ICT/KTH Forum 120, 164 40, Kista, Sweden

    Axel Jantsch

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  1. Konstantinos Tatas
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  2. Kostas Siozios
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  4. Axel Jantsch
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Correspondence to Konstantinos Tatas .

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Tatas, K., Siozios, K., Soudris, D., Jantsch, A. (2014). Power and Thermal Effects and Management. In: Designing 2D and 3D Network-on-Chip Architectures. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4274-5_4

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  • DOI: https://doi.org/10.1007/978-1-4614-4274-5_4

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