Abstract
The first chapter introduces the fundamental Network-on-Chip (NoC) concepts starting with the motivation that caused the paradigm shift from bus-based to NoC-based architectures. Similarities and differences between NoCs and computer networks are discussed. Furthermore, the components of a NoC-based System-on-Chip (SoC) are introduced and the NoC functionality is outlined in terms of the OSI layer structure. A significant part of this chapter is spent explaining both the benefits and challenges of adopting NoC as the SoC communication infrastructure. Finally, current research topics in the area are classified.
Keywords
- Global Asynchronous Local Synchronous
- Global Wire
- Embed Memory Block
- Interconnection Infrastructure
- Single Chip Multiprocessor
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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G. Moore, No Exponential is Forever: But “Forever” Can Be Delayed! [semiconductor industry], Solid-State Circuits Conference (ISSCC), pp. 20–23, 2003
ITRS 2011.http://www.itrs.net
V. Lo, S. Rajopadhye, S. Gupta, D. Keldsen, M. Mohamed, B. Nitzberg, J. Telle, X. Zhong, OREGAMI: tools for mapping parallel computations to parallel architectures. Int. J. Parallel Programming 20(3), 237–270 (1991)
S. Murali, G. De Micheli, SUNMAP: a tool for automatic topology selection and generation for NoCs, Design Automation Conference (DAC), pp. 914–919, 2004
Stanford CPU database. http://cpudb.stanford.edu
B. Ackland, A. Anesko, D. Brinthaupt, S. Daubert, A. Kalavade, J. Knobloch, E. Micca, M. Moturi, C. Nicol, J. O’Neill, J. Othmer, E. Sackinger, K. Singh, J. Sweet, C. Terman, J. Williams, A single chip, 1.6-billion, 16-b MAC/s multiprocessor DSP. IEEE J. Solid-State Circuits 35(3), 412–424 (2000)
A comparison of Network-on-Chip and Busses, white paper by Arteris Corp. http://www.design-reuse.com/articles/10496/a-comparison-of-network-on-chip-and-busses.html
T. Bjerregaard, S. Mahadevan, A survey of research and practices of Network-on-chip. ACM Comput. Surv. 38(1), Article 1 (2006)
V. Pavlidis, E. Friedman, Three-Dimensional Integrated Circuit Design (Morgan Kaufmann, San Francisco, 2010)
V. Rantala, T. Lehtonen, J. Plosila, Network on Chip Routing Algorithms, TUCS Technical Report, Turku Center for Computer Science, No. 779, August 2006
NoC Interconnect Improves SoC Economics, Objective Analysis - Semiconductor Market Research, 2011. http://www.objective-analysis.com/uploads/NoC_Interconnect_Improves_SoC_Economics_-_Objective_Analysis.pdf
A. Jantch, H. Tenhunen, Networks on Chip (Springer, Berlin, 2003)
J.-J. Lecler, G. Baillieu, Application driven network-on-chip architecture exploration & refinement for a complex SoC. J. Des. Autom. Embed. Syst. 15(2), 133–158 (2011)
G. De Micheli, L. Benini, Networks on Chips: Technology and Tools (Systems on Silicon) (Morgan Kaufmann, San Francisco, 2006)
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Tatas, K., Siozios, K., Soudris, D., Jantsch, A. (2014). Network-on-Chip Technology: A Paradigm Shift. In: Designing 2D and 3D Network-on-Chip Architectures. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4274-5_1
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DOI: https://doi.org/10.1007/978-1-4614-4274-5_1
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