Abstract
This chapter describes the various features involved in specifying the design intent for a low power design and how these are specified for detailed implementation.
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Notes
- 1.
Most designs would use only a subset of these features.
- 2.
A valid signal implies a logic-0 (VSS) or a logic-1 (VDD) for the receiving block, whereas an invalid signal may be a non-driven signal which can just be floating and/or be at an arbitrary intermediate voltage value.
- 3.
A CMOS cell with input values which are not “near” VSS or “near” VDD can result in increased power dissipation. This is because both the pull-up (NMOS) and the pull-down (PMOS) stages of the CMOS logic can be on simultaneously resulting in large crowbar current.
- 4.
Crowbar current is the current flowing due to complementary PMOS and NMOS structures being on simultaneously.
- 5.
Liberty file.
- 6.
Coarse-grain and fine-grain distribution of switches is described in Sect. 6.7. This section also describes fine-grain power gating where the switch can be applied to turn off individual cells.
- 7.
Rush currents are described in detail in Sect. 7.6.
- 8.
The VDD pin, even though it exists as a pin on the cell, does not typically connect to anything within the cell.
- 9.
Process, Voltage, Temperature.
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© 2013 Springer Science+Business Media New York
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Chadha, R., Bhasker, J. (2013). Design Intent for Power Management. In: An ASIC Low Power Primer. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4271-4_5
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DOI: https://doi.org/10.1007/978-1-4614-4271-4_5
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