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Low Cost C-Testable Finite Field Multiplier Architectures

Chapter

Abstract

Design for Test (DFT) techniques attempt to improve access to the internal state of the crypto hardware either by improving control of internal nodes from the primary inputs or by improving observation capability of values on internal nodes at the primary outputs or both. Scan-based test is a powerful Design-For-Testability (DFT) technique.

Keywords

Sequence Vector Test Vector Fault Coverage Automatic Test Pattern Generation EXOR Part 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.Department of Computer ScienceUniversity of BristolBristolUK

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