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Circuit Design for Reliability pp 175–205Cite as

Power-Gating for Leakage Control and Beyond

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Abstract

The need of reliable nanometric integrated circuits is driving the EDA community to develop new automated design techniques in which power consumption and variability are central objectives of the optimization flow.

Although several Design-for-Low-Power and Design-for-Variability options are already available in modern EDA suites, the contrasting nature of the two metrics makes their integration extremely challenging. Most of the approaches used to compensate and/or mitigate circuit variability (e.g., Dynamic Voltage Scaling and Adaptive Body Biasing) are, in fact, intrinsically power inefficient, as they exploit the concept of redundancy, which is known to originate power overhead.

In this work, we introduce possible solutions for concurrent leakage minimization and variability compensation. More specifically, we propose Power-Gating as a mean for simultaneously controlling static power consumption and mitigating the effects induced by two of the most insidious sources of variability, namely, Process Variations (PV) due to uncertainties in the manufacturing and Transistor Aging due to Negative Bias Temperature Instability (NBTI).

We show that power-gating, when implemented through the insertion of dedicated switches (called sleep transistors), has a double effect: On one hand, when sleep transistors are enhanced with tunable features, it acts as a natural supply-voltage regulator, which implements a control knob for PV compensation; on the other hand, during the idle periods, it makes the circuits immune to NBTI-induced aging.

We describe optimization techniques for the integration of a new concept of power-gating into modern sub-45 nm design flows, that is, Variation-Aware Power-Gating. The experimental results we have obtained are extremely promising, since they show 100 % timing yield under the presence of PV and circuit lifetime extension of more than 5× in the presence of NBTI.

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Authors and Affiliations

  1. Dip. di Automatica e Informatica, Politecnico di Torino, 10129, Torino, Italy

    Andrea Calimera, Alberto Macii, Enrico Macii & Massimo Poncino

Authors
  1. Andrea Calimera
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  2. Alberto Macii
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  3. Enrico Macii
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  4. Massimo Poncino
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Corresponding author

Correspondence to Enrico Macii .

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Editors and Affiliations

  1. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Rio Grande do Sul, Brazil

    Ricardo Reis

  2. School of ECEE, Arizona State University, Tempe, USA

    Yu Cao

  3. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Rio Grande do Sul, Brazil

    Gilson Wirth

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Calimera, A., Macii, A., Macii, E., Poncino, M. (2015). Power-Gating for Leakage Control and Beyond. In: Reis, R., Cao, Y., Wirth, G. (eds) Circuit Design for Reliability. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4078-9_9

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  • DOI: https://doi.org/10.1007/978-1-4614-4078-9_9

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  • Online ISBN: 978-1-4614-4078-9

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