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Compact Modeling of BTI for Circuit Reliability Analysis

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Circuit Design for Reliability

Abstract

The aging process due to Bias Temperature Instability (BTI) is a key limiting factor of circuit lifetime in contemporary CMOS design. Threshold voltage shift induced by BTI is a strong function of stress voltage and temperature. Furthermore, BTI consists of both stress and recovery phases, depending on the dynamic stress conditions. This behavior poses a unique challenge for long-term aging prediction for a wide range of stress patterns encountered in today’s circuits. Traditional approaches usually resort to an average, constant stress waveform to simplify the lifetime prediction. They are efficient, but fail to capture the reality of circuit operation, especially under Dynamic Voltage Scaling (DVS) or in analog/mixed signal designs where the stress waveform is much more random. In this chapter, we present a suite of modeling solutions that enable aging simulation under all dynamic stress conditions. The key innovation of this chapter is to develop compact models of BTI when the stress voltage is varying. The results cover the underlying physics of two leading mechanisms, Reaction–Diffusion (R–D) and Trapping/Detrapping (T–D). Moreover, silicon validation of these models is performed at 45 and 65 nm technology nodes, at both device and circuit levels. Leveraging the newly developed BTI models under DVS and random input waveforms, efficient aging simulation is demonstrated in representative digital and analog circuits. Our proposed work provides a general and comprehensive solution to circuit aging analysis under random stress patterns.

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Authors and Affiliations

  1. School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, Arizona, 85287, USA

    Ketul B. Sutaria, Jyothi B. Velamala, Athul Ramkumar & Yu Cao

Authors
  1. Ketul B. Sutaria
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  2. Jyothi B. Velamala
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  3. Athul Ramkumar
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  4. Yu Cao
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Corresponding author

Correspondence to Yu Cao .

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Editors and Affiliations

  1. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Rio Grande do Sul, Brazil

    Ricardo Reis

  2. School of ECEE, Arizona State University, Tempe, USA

    Yu Cao

  3. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Rio Grande do Sul, Brazil

    Gilson Wirth

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Sutaria, K.B., Velamala, J.B., Ramkumar, A., Cao, Y. (2015). Compact Modeling of BTI for Circuit Reliability Analysis. In: Reis, R., Cao, Y., Wirth, G. (eds) Circuit Design for Reliability. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4078-9_6

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  • DOI: https://doi.org/10.1007/978-1-4614-4078-9_6

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