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Variability-Aware Clock Design

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Circuit Design for Reliability

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Abstract

High-performance clock network design has been a challenge for many years due to the drastically increasing effect of process variability. In addition, tight power budgets have lowered supply voltage levels which make designs more sensitive to noise. Together, variability and noise present a colossal challenge to clock designers in order to meet timing, yield, and power simultaneously. This chapter discusses the different strategies that designers use to ameliorate variability and noise problems in clock network design.

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Author information

Authors and Affiliations

  1. University of California Santa Cruz, 1156 High St. MS SOE3, Santa Cruz, CA, 95064, USA

    Matthew R. Guthaus

  2. UFRGS, Av. Bento Gonçalves, 9500 - Campus do Vale - Bloco IV, Porto Alegre, RS, 91509-900, Brazil

    Gustavo Wilke

Authors
  1. Matthew R. Guthaus
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  2. Gustavo Wilke
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Correspondence to Matthew R. Guthaus .

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Editors and Affiliations

  1. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Rio Grande do Sul, Brazil

    Ricardo Reis

  2. School of ECEE, Arizona State University, Tempe, USA

    Yu Cao

  3. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Rio Grande do Sul, Brazil

    Gilson Wirth

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Guthaus, M.R., Wilke, G. (2015). Variability-Aware Clock Design. In: Reis, R., Cao, Y., Wirth, G. (eds) Circuit Design for Reliability. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4078-9_12

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  • DOI: https://doi.org/10.1007/978-1-4614-4078-9_12

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