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Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

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Circuit Design for Reliability

Abstract

FinFETs have emerged as alternatives to conventional bulk MOSFETs in scaled technologies due to superior gate control of the channel, lower short channel effects and higher scalability. However, width quantization in FinFETs constrains the design space of FinFET-based circuits, especially SRAMs in which transistor sizing is critical for the circuit robustness. The adverse effects of width quantization can be mitigated by appropriate device-circuit co-design of FinFET-based memories. This chapter describes some of such techniques with an emphasis on the device-circuit interactions associated with each methodology. The impact of different technology options in FinFETs like gate-underlap, fin orientation, fin height, gate workfunction and independent control of the gates on the stability, power and performance of 6 T SRAMs is discussed.

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Authors and Affiliations

  1. School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907, USA

    Sumeet Kumar Gupta & Kaushik Roy

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  1. Sumeet Kumar Gupta
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  2. Kaushik Roy
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Correspondence to Kaushik Roy .

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Editors and Affiliations

  1. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Rio Grande do Sul, Brazil

    Ricardo Reis

  2. School of ECEE, Arizona State University, Tempe, USA

    Yu Cao

  3. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Rio Grande do Sul, Brazil

    Gilson Wirth

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Gupta, S.K., Roy, K. (2015). Low Power Robust FinFET-Based SRAM Design in Scaled Technologies. In: Reis, R., Cao, Y., Wirth, G. (eds) Circuit Design for Reliability. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4078-9_11

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  • DOI: https://doi.org/10.1007/978-1-4614-4078-9_11

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  • Online ISBN: 978-1-4614-4078-9

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