Circuit Techniques to Assist SRAM Cell: Local Assist Circuitry

Abstract

SRAM cell design is a critical feature in achieving technology scaling benefits for SOC designs. The reduced voltage level and the utilization of low-power (LP) CMOS technologies are required for the low leakage SRAM cell design. The reduction in VDD and the increased threshold voltage aggravates variability for the SRAM cell design. This result in degradation of Iread, read static noise margin (SNM), and write-ability (WM) of SRAM cell as discussed in Chap. 2. The design optimizations done in improving one parameter often ends up in worsening the other. Read SNM (functionality) is of utmost concern and SRAM design techniques to improve the read SNM come at the expense of detrimental impact on Iread. Therefore, conventional SRAM 6T cell design is a highly constrained area-stability-power-performance trade off design effort. Local assist circuit techniques with hierarchical bit-lines are becoming increasingly necessary to maintain the SRAM cell functionality and to achieve performance target at the cost of a minimal area increase. The use of local assist circuits alleviates the complex design trade off effort of SRAM cell design. This chapter discusses various circuit assist techniques to alleviate the complex design trade off of SRAM cell design. The different assist techniques discussed are as follows.