Abstract
The minimum supply voltage for SRAM cell is limited by write failures (write-ability) or read disturb failures (cell stability). In the previous chapter, various SRAM cells are discussed which offer better variability resilience compared to the SRAM 6T cell and enable low VDD operation. SRAM 6T cell functionality is highly dependent on the supply voltage. The voltage optimization can impact the write failures and the read disturb failures significantly. In this chapter, dynamic voltage optimization techniques, are studied for realizing low VDD operation with the conventional SRAM 6T cell while maintaining sufficient READ/WRITE margins.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
G. Chen et al., Crosshars SRAM—an adaptive memory for mitigating parametric failures. in Proceedings of IEEE European Solid State Circuits Conference (ESSCIRC), pp. 366–369 (2010)
Y. Fujimura et al., A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149um2 cell in 32 nm high-K metal-gate CMOS. in Proceedings of International Solid State Conference (ISSCC), pp. 348–350, Feb 2010
O. Hirabayashi et al., A process-variation-tolerant dual-power-supply SRAM with 0.179um2 Cell in 40nm CMOS using level-programmable wordline driver. in Proceedings of International Solid State Conference (ISSCC), pp. 458–459, Feb 2009
M. Khellah et al., Word line and bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65 nm CMOS designs. Symposium on VLSI circuits digest of technical papers, pp. 9–10 (2006)
K. Nii et al., A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. Symposium on VLSI circuits digest of technical papers, pp. 212–213 (2008)
S. Ohbayashi et al., A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits. IEEE J. Solid State Circ. 42(4), 820–829 (2007)
A. Raychowdhury et al., PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. in Proceedings of International Solid State Conference (ISSCC), pp. 352–353 (2010)
M. Sinangil et al., Reconfigurable 8T ultra-dynamic voltage scalable (U-DVS) SRAM in 65 nm CMOS. IEEE J. Solid-State Circ. 44(11), 3163–3173 (2009)
M. Sinangil et al., A 28 nm high density 6T SRAM with optimized peripheral- assist circuits for operation down to 0.6 V. in Proceedings of International Solid State Conference (ISSCC), pp. 260–261, Feb 2011
V. Sharma et al., A 4.4pJ/Access 80Â MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier redundancy. IEEE J. Solid State Circ. 46(10) (2010)
V. Sharma et al., 8T SRAM with mimicked negative bit-lines and charge limited sequential sense amplifier for wireless sensor nodes. in Proceedings of IEEE European Solid State Circuits Conference (ESSCIRC), pp. 531–534 (2011)
V. Sharma et al., Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM cell, Design automation and test in Europe (DATE), Dresden, 11–17 March 2012
M. Yabuuchi et al., A 45 nm low-standby-power embedded sram with improved immunity against process and temperature variations. in Proceeding of ISSCC, pp. 326–327, 606 (2007)
M. Yabuuchi et al., A 45NM 0.6 V cross-point 8T SRAM with negative read/write assist. Symposium on VLSI circuits digest of technical papers, pp. 158–159, (2009)
M. Yamaoka et al., A 300 MHz 25uA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. in Proceedings of International Solid State Conference (ISSCC), Section 27.2 (2004)
M. Yamaoka et al., 90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. IEEE J. Solid State Circ. 41(3), 705–711 (2006)
K. Zhang et al., A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. IEEE J. Solid State Circ. 41(1), 146–151 (2006)
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer Science+Business Media New York
About this chapter
Cite this chapter
Sharma, V., Catthoor, F., Dehaene, W. (2013). Adaptive Voltage Optimization Techniques: Low Voltage SRAM Operation. In: SRAM Design for Wireless Sensor Networks. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4039-0_3
Download citation
DOI: https://doi.org/10.1007/978-1-4614-4039-0_3
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-4038-3
Online ISBN: 978-1-4614-4039-0
eBook Packages: EngineeringEngineering (R0)