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Abstract

As shown in Chap. 2, Wireless Sensor Network (WSN) nodes must be equipped with fully integrated time references with an accuracy of the order of 1% and a power consumption lower than 100 μW. Recently, much work has been devoted to implementing fully integrated time references in standard microelectronic technologies. As shown in Chap. 3, the inaccuracy of several of them is low enough for WSN applications, but they need either a too high power consumption or a very accurate process characterization, with a consequent limitation of their practical use.

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Notes

  1. 1.

    A mobility-based time reference is presented in [1] but measurement results from only one sample are reported, which do not give any information about the spread.

  2. 2.

    Geometric factors in (4.27) (W 1, L 1 and the area of capacitors C A and C B ) are also affected by process spread. However, their effect on T osc can be neglected if sufficiently large devices are employed.

  3. 3.

    An external opamp (LTC1053) is used only for testing purpose.

  4. 4.

    Note that a pad with large ESD protection diodes and an external opamp are connected to one end of R 1. The parasitic current through R 1 is the sum of the leakage currents of the ESD diodes and of the input bias current of the opamp.

  5. 5.

    The area labelled as “capacitors” in Fig. 4.10 also contains also transistors M 1 and M 3 of the current reference, which are required to match MOS capacitors C A and C B .

  6. 6.

    The values used for αμ were obtained at − 40 ∘ C and 85 ∘ C from the slope of the average frequency characteristic in Fig. 4.14.

References

  1. Blauschild R (1994) An integrated time reference. ISSCC Dig. of Tech. Papers, pp 56–57

    Google Scholar 

  2. Tsividis Y (2003) Operation and modeling of the Mos transistor, 2nd edn. Oxford University Press, New York, p 12

    Google Scholar 

  3. Tsividis YP (1994) Integrated continuos-time filter design – an overview. IEEE J Solid State Circ 29(3):166–176

    Article  Google Scholar 

  4. Sansen W, Op’t Eynde F, Steyaert M (1988) A CMOS temperature-compensated current reference. IEEE J Solid State Circ 23(3):821–824

    Article  Google Scholar 

  5. Jeon D, Burk D (1989) MOSFET electron inversion layer mobilities-a physically based semi-empirical model for a wide temperature range. IEEE Trans Electron Dev 36(8):1456–1463. DOI 10.1109/16.30959

    Article  Google Scholar 

  6. Ghani T, Mistry K, Packan P, Thompson S, Stettler M, Tyagi S, Bohr M (2000) Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors. In: 2000 Symposium on VLSI Circuits Dig. Tech. Papers, pp 174–175. DOI 10.1109/VLSIT.2000.852814

    Google Scholar 

  7. Lo SH, Buchanan D, Taur Y, Wang W (1997) Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s. IEEE Electron Dev Lett 18(5):209–211. DOI 10.1109/55.568766

    Article  Google Scholar 

  8. Mukhopadhyay S, Neau C, Cakici RT, Agarwal A, Kim CH, Roy K (2003) Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans VLSI Syst 11(4):716–730

    Article  Google Scholar 

  9. O’Halloran M, Sarpeshkar R (2004) A 10-nW 12-bit accurate analog storage cell with 10-aA leakage. IEEE J Solid State Circ 39(11):1985–1996. DOI 10.1109/JSSC.2004. 835817

    Article  Google Scholar 

  10. Wang TJ, Ko CH, Chang SJ, Wu SL, Kuan TM, Lee WC (2008) The effects of mechanical uniaxial stress on junction leakage in nanoscale CMOSFETs. IEEE Trans Electron Dev 55(2):572–577. DOI 10.1109/TED.2007.912363

    Article  Google Scholar 

  11. Sedra AS, Smith KC (1998) Microelectronics circuits, 4th edn. Oxford University Press, New York

    Google Scholar 

  12. Tsividis Y (2003) Operation and modeling of the MOS transistor, 2nd edn. Oxford University Press, New York, NY

    Google Scholar 

  13. Sebastiano F, Breems L, Makinwa K, Drago S, Leenaerts D, Nauta B (2009) A low-voltage mobility-based frequency reference for crystal-less ULP radios. IEEE J Solid State Circ 44(7):2002–2009

    Article  Google Scholar 

  14. Annema AJ, Nauta B, van Langevelde R, Tuinhout H (2005) Analog circuits in ultra-deep-submicron CMOS. IEEE J Solid State Circ 40(1):132–143. DOI 10.1109/ JSSC.2004.837247

    Article  Google Scholar 

  15. Gregor R (1992) On the relationship between topography and transistor matching in an analog CMOS technology. IEEE Trans Electron Dev 39(2):275–282

    Article  Google Scholar 

  16. Tuinhout H, Vertregt M (1997) Test structures for investigation of metal coverage effects on mosfet matching. In: Proceedings of IEEE International Conference on Microelectronic Test Structures, ICMTS 1997, pp 179–183. DOI 10.1109/ICMTS. 1997.589386

    Google Scholar 

  17. Tuinhout H, Vertregt M (2001) Characterization of systematic MOSFET current factor mismatch caused by metal CMP dummy structures. IEEE Trans Semicond Manuf 14(4):302–310. DOI 10.1109/66.964317

    Article  Google Scholar 

  18. Bakker A, Huijsing J (1996) Micropower CMOS temperature sensor with digital output. IEEE J Solid State Circ 31(7):933–937

    Article  Google Scholar 

  19. Aita AL, Pertijs MA, Makinwa KAA, Huijsing JH (2009) A CMOS smart temperature sensor with a batch-calibrated inaccuracy of ± 0. 25 ∘ C (3σ) from − 70 to 130  ∘ C. In: ISSCC Dig. of Tech. Papers

    Google Scholar 

  20. Liu C, McNeill J (2004) Jitter in oscillators with 1/f noise sources. Proc ISCAS 1:I–773–6. DOI 10.1109/ISCAS.2004.1328309

    Google Scholar 

  21. Meijer G, Wang G, Fruett F (2001) Temperature sensors and voltage references implemented in CMOS technology. IEEE Sensor J 1(3):225–234. DOI 10.1109/JSEN. 2001.954835

    Article  Google Scholar 

  22. Sebastiano F, Breems L, Makinwa K, Drago S, Leenaerts D, Nauta B (2011) Effects of packaging and process spread on a mobility-based frequency reference in 0.16-μm CMOS. In: Proceedings of ESSCIRC, pp 511–514

    Google Scholar 

  23. Duarte D, Geannopoulos G, Mughal U, Wong K, Taylor G (2007) Temperature sensor design in a high volume manufacturing 65nm CMOS digital process. In: Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp 221–224. DOI 10.1109/CICC.2007.4405718

    Google Scholar 

  24. Lakdawala H, Li Y, Raychowdhury A, Taylor G, Soumyanath K (2009) A 1.05 V 1.6 mW 0.45  ∘ C 3σ-resolution ΣΔ-based temperature sensor with parasitic-resistance compensation in 32 nm CMOS. IEEE J Solid State Circ (12):3621–3630

    Google Scholar 

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Sebastiano, F., Breems, L.J., Makinwa, K.A.A. (2013). A Mobility-Based Time Reference. In: Mobility-based Time References for Wireless Sensor Networks. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3483-2_4

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  • DOI: https://doi.org/10.1007/978-1-4614-3483-2_4

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