Integrated Prototypes and Experimental Results

Abstract

This chapter discusses the implementation of two integrated circuit (IC) prototypes with the objective of evaluating their performance and functionality. The first circuit concerns the two-stage inverter-based self-biased amplifier presented and described in Sect. 4.2 The second prototype concerns the 7-bit 1 GS/s two-way interleaved pipeline ADC, which was presented in Chap. 5. For each prototype, a floorplan and layout will be shown, and some design and layout considerations will be given. Equally, the designed printed circuit board (PCB) and the respective test setup used for each circuit evaluation will be presented. Each IC prototype section will end with the experimental results achieved and a comparison will be carried out with the state-of-the-art. Regarding the technology employed to design and implement the circuits, a standard digital 0.13 ${\upmu}$m 1.2 V 1P-8M CMOS process has been used. No special device options such as, low- or high-$V_T$, twin- or triple-well or low leakage devices, etc., were used. For capacitors, the technology’s Metal-Insulator-Metal (MIM) capacitors, MOS capacitors, and our design group’s proprietary Metal-Oxide-Metal (MOM) capacitors were used.