Design of a 7-bit 1 GS/s CMOS Two-Way Interleaved Pipeline ADC

Part of the Analog Circuits and Signal Processing book series (ACSP)


This chapter discusses the design of a 7-bit 1 GS/s time-interleaved pipeline ADC, implemented in a standard digital 0.13 \({\upmu} \)m CMOS technology. All the sub-blocks used in the design of the ADC are also described in this chapter. Furthermore, specifications for the design and the architecture of the ADC are presented. One of the main objectives of this work was to integrate the proposed current-mode reference shifting (CMRS) MDAC circuit (Sect. 3.2) and verify its functionality in a working ADC structure. As secondary objectives, the proposed amplifier and flash quantizer (Chap. 4) circuits are also to be integrated in this prototype, in order to verify their performance, functionality, and usefulness in a pipeline ADC environment. Notice that, with the integration of both the proposed CMRS-MDAC and flash quantizer, the designed ADC precludes reference voltage circuitry, such as voltage buffers, decoupling capacitors, and damping resistors.


Clock Generator Clock Signal Output Buffer Pipeline Stage NMOS Transistor 
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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Centre of Technology and SystemsUniversidade Nova de LisboaCaparicaPortugal
  2. 2.Department of Electrical EngineeringUniversidade Nova de LisboaCaparicaPortugal
  3. 3. Departamento de Física, Faculdade de CiênciasUniversidade de LisboaLisboaPortugal

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