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Design of a 7-bit 1 GS/s CMOS Two-Way Interleaved Pipeline ADC

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Reference-Free CMOS Pipeline Analog-to-Digital Converters

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Abstract

This chapter discusses the design of a 7-bit 1 GS/s time-interleaved pipeline ADC, implemented in a standard digital 0.13 \({\upmu} \)m CMOS technology. All the sub-blocks used in the design of the ADC are also described in this chapter. Furthermore, specifications for the design and the architecture of the ADC are presented. One of the main objectives of this work was to integrate the proposed current-mode reference shifting (CMRS) MDAC circuit (Sect. 3.2) and verify its functionality in a working ADC structure. As secondary objectives, the proposed amplifier and flash quantizer (Chap. 4) circuits are also to be integrated in this prototype, in order to verify their performance, functionality, and usefulness in a pipeline ADC environment. Notice that, with the integration of both the proposed CMRS-MDAC and flash quantizer, the designed ADC precludes reference voltage circuitry, such as voltage buffers, decoupling capacitors, and damping resistors.

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Notes

  1. 1.

    Corners considered: \({ tt}\), \({ ss}\), and \({ ff}\) for process; 1.2 V\({\pm }\)5 % for supply voltage, and \(-40^\circ \), \(27^\circ \), and \(85^\circ \) for temperature.

  2. 2.

    Occurs during the amplification phase, where \(C_{1j}\) and \(C_{2j}\), \(j=\{1,2\}\) are associated in series, and the equivalent capacitance becomes half the unit capacitance (150 fF), i.e., becomes 75 fF.

  3. 3.

    Notice that, in a future design of this ADC, as an intellectual property (IP) product, these two currents would be generated on-chip either using an SC reference current generator [165] or using a replica MDAC together with a servo-loop (see Appendix A).

  4. 4.

    The RS Bias circuit is shared between channels to reduce power consumption and circuit overhead, and therefore provides current for reference shifting for both MDACs.

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Correspondence to Michael Figueiredo .

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Figueiredo, M., Goes, J., Evans, G. (2013). Design of a 7-bit 1 GS/s CMOS Two-Way Interleaved Pipeline ADC. In: Reference-Free CMOS Pipeline Analog-to-Digital Converters. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3467-2_5

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  • DOI: https://doi.org/10.1007/978-1-4614-3467-2_5

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  • Online ISBN: 978-1-4614-3467-2

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