Abstract
In the first section of this chapter, a 1.5-bit flash quantizer is proposed. This fully differential flash quantizer has built-in thresholds, made possible by employing inverter structures as input devices. Self-biasing techniques are employed for enhanced PVT robustness. Various analyses (confirmed with simulations) are carried out to describe the circuit’s functionality, such as, kickback noise, regeneration time, metastability, offset, sensitivity to common-mode variations, and finally, a working proof of a pipeline ADC that employs the proposed circuit in all stages is given. A design procedure is also described and the section is concluded with a performance summary and a comparative table. The second section of this chapter presents a two-stage amplifier with enhanced performance. Energy efficiency is improved by using inverter-input structures, which effectively double the transconductance of the circuit for the same current. Self-biasing is employed in both stages for improved PVT robustness and further power reduction. The analyses carried out include differential-mode and common-mode feedback, noise, offset, slew rate, input-output ranges, and some considerations are given what concerns the amplifier’s class of operation. Finally, guidelines are given for a successful design and a genetic algorithm optimization procedure is briefly described.
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Notes
- 1.
Not to be confused with the threshold voltage of a transistor.
- 2.
With an input exactly equal to the threshold voltage, the regeneration time would be infinitely long, leading to a situation of metastability.
- 3.
The averaged GBW is used here as an approximation, to simplify the calculations.
- 4.
Generally, an \(N\)-node system (excluding DC nodes and input node) has \(N\) initial conditions, which correspond to \(N\) poles [71]. In this case, we have a 3-node system, hence a 3-pole system.
- 5.
\(A_{{ DC}}f_{{ d}} =\) GBW only in single pole amplifiers or when a sufficient phase margin (\({\mathrm PM}>60^\circ \)) is obtained for multi-pole amplifiers.
- 6.
This value was extracted from PVT corner simulations of the amplifier that is presented in Sect. 6.1.
- 7.
\(K_{N,P}\) represents \(\mu _{N,P} C_{ox}.\)
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© 2013 Springer Science+Business Media New York
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Figueiredo, M., Goes, J., Evans, G. (2013). Application of Circuit Enhancement Techniques to ADC Building Blocks. In: Reference-Free CMOS Pipeline Analog-to-Digital Converters. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3467-2_4
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DOI: https://doi.org/10.1007/978-1-4614-3467-2_4
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