Parallel Pseudo-Exhaustive and Low Power Delay Testing of VLSI Systems

Abstract

The aim of the paper is to conduct parallel delay testing of modules with different input capacities in a SOC, using mutual BIST pattern generator; especially iterative system realisations well suited for VLSI fabrication technologies. The quality of timing optimised and high performance digital VLSI systems is assured only through delay testing. A unique accumulator based Iterative Pseudo-Exhaustive Two-Pattern (IPET) generator for parallel delay BIST is presented. Generally, the accumulator belongs to the data-path of the SOC. Hence, IPET test can be generated using micro-code self-test strategy. Reduced hardware overhead due to accumulator based design and test time due to parallelism is found to be beneficial. A CMOS implementation of Low Power Architecture for delay testing is carried out, which reduces test power and test time. These architectures can be used as efficient chip-level designs for high speed and low power BIST of SOCs.