Abstract
The effect of temperature on SiGe hetero-gate raised buried oxide drain Tunnel FET electrical parameters like tunnelling bandgap, threshold voltage, subthreshold swing, etc. are discussed in this paper. A modified SOI based Silicon hetero-gate TFET structure has been used. The proposed device is almost free from short channel effects. The simulation is performed using Synopsys 2D TCAD tools where non local band-to-band tunnelling is applied.
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Acknowledgments
This work was supported by ALL INDIA COUNCIL FOR TECHNICAL EDUCATION (AICTE), under Grant 8023/BOR/RID/RPS-253/2008-09.
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das, M., Bhowmick, B. (2013). Effect of Temperature on Si-Ge Hetero-Gate Raised Buried Oxide Drain Tunnel FET Electrical Parameters. In: Das, V. (eds) Proceedings of the Third International Conference on Trends in Information, Telecommunication and Computing. Lecture Notes in Electrical Engineering, vol 150. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3363-7_31
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DOI: https://doi.org/10.1007/978-1-4614-3363-7_31
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