Abstract
In the preceding chapters, we assumed the clock to be ideal, i.e., they transition from 0 to 1 and vice versa instantaneously (have a rectangular waveform); they reach all the flops in the design at the same time (all edges align) and there is no delay between the clock generation circuit and the place where the clock is actually consumed. In reality, clocks are never ideal.
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© 2013 Springer Science+Business Media New York
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Gangadharan, S., Churiwala, S. (2013). Other Clock Characteristics. In: Constraining Designs for Synthesis and Timing Analysis. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3269-2_8
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DOI: https://doi.org/10.1007/978-1-4614-3269-2_8
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