Abstract
Most complex designs require more than one clock for its functioning. When there are multiple clocks in a design, they would need to interact or share a relationship. Asynchronous clocks are clock signals that don’t share a fixed phase relationship. Having only asynchronous clocks in the design makes it really hard to meet setup and hold requirements when multiple clock domains are interacting. We will explain about this in Chap. 7 as to why it is so. Synchronous clocks share a fixed phase relationship. More often than not synchronous clocks originate from the same source.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer Science+Business Media New York
About this chapter
Cite this chapter
Gangadharan, S., Churiwala, S. (2013). Generated Clocks. In: Constraining Designs for Synthesis and Timing Analysis. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3269-2_6
Download citation
DOI: https://doi.org/10.1007/978-1-4614-3269-2_6
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-3268-5
Online ISBN: 978-1-4614-3269-2
eBook Packages: EngineeringEngineering (R0)