Innovative Structures for Routing and Configuration

  • Pierre-Emmanuel Gaillardon
  • Ian O’Connor
  • Fabien Clermidy


The goal of this chapter is to illustrate how emerging technologies can help to improve performance metrics of conventional Field-Programmable Gate Arrays structures. It is widely recognized that in traditional FPGAs, both the memory and the routing circuitry (with 43% of area for each contribution) represent the principal bottleneck to scaling and performance increase. In this context, we investigated 3D integration techniques for passive and active devices. The technologies surveyed will be a resistive memory technology, monolithic 3D integration and a vertical 1D transistor technology.


Data Path Cross Point SRAM Cell Configuration Memory Resistive Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Xilinx Virtex-6 FPGA family overview, 24 March 2011
  2. 2.
    J. McCollum, H.-S. Chen, F. Hawley, Non-volatile programmable memory cell for programmable logic array, US Patent No. 0,064,484, 2007Google Scholar
  3. 3.
    Emerging Research Devices and Materials Chapters, Updated Editions, International Technology Roadmap for Semiconductors (2010).
  4. 4.
    H.J. Hovel, J.J. Urgell, Switching and memory characteristics of ZnSe–Ge heterojunctions. J. Appl. Phys. 42, 5076 (1971)CrossRefGoogle Scholar
  5. 5.
    I.G. Baek, M.S. Lee, S. Seo, M.J. Lee, D.H. Seo, D.-S. Suh, J.C. Park, S.O. Park, H.S. Kim, I.K. Yoo, U.-I. Chung, J.T. Moon, Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses, in International Electron Devices Meeting. pp. 587–590, 13–15 Dec 2004Google Scholar
  6. 6.
    K. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, Y. Sugiyama, Low power and high speed switching of Ti-doped NiO ReRAM under the unipolar voltage source of less than 3 V, in International Electron Devices Meeting. pp. 767–770, 10–12 Dec 2007Google Scholar
  7. 7.
    C. Nauenheim, C. Kugeler, S. Trellenkamp, A. Rudiger, and R. Waser, Phenomenological considerations of resistively switching TiO2 in nano crossbar arrays, in 10th International Conference on ULIS. pp. 135–138, 18–20 March 2009Google Scholar
  8. 8.
    H.Y. Lee, Y.S. Chen, P. S. Chen, T. Y. Wu, F. Chen, C.C. Wang, P.J. Tzeng, M.-J. Tsai, C. Lien, Low-power and nanosecond switching in robust hafnium oxide resistive memory with a thin Ti cap. IEEE Electron Device Lett. 31(1), 44–46, January (2010)CrossRefGoogle Scholar
  9. 9.
    W.C. Chien, Y.C. Chen, K.P. Chang, E.K. Lai, Y.D. Yao, P. Lin, J. Gong, S.C. Tsai, S.H. Hsieh, C.F. Chen, K.Y. Hsieh, R. Liu, C.-Y. Lu, Multi-level operation of fully CMOS compatible WOX resistive random access memory (RRAM), International Memory Workshop. pp. 1–2, 10–14 May 2009Google Scholar
  10. 10.
    P. Zhou, H.J. Wan, Y.L. Song, M. Yin, H.B. Lu, Y.Y. Lin, S. Song, R. Huang, J.G. Wu, M.H. Chi, A systematic investigation of TiN/CuxO/Cu RRAM with long retention and excellent thermal stability, in International Memory Workshop. pp. 1–2, 10–14 May 2009Google Scholar
  11. 11.
    Z. Wei, Y. Kanzawa, K. Arita, Y. Katoh, K. Kawai, S. Muraoka, S. Mitani, S. Fujii, K. Katayama, M. Iijima, T. Mikawa, T. Ninomiya, R. Miyanaga, Y. Kawashima, K. Tsuji, A. Himeno, T. Okada, R. Azuma, K. Shimakawa, H. Sugaya, T. Takagi, R. Yasuhara, K. Horiba, H. Kumigashira, M. Oshima, Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism, in International electron devices meeting. pp. 1–4, 15–17 Dec 2008Google Scholar
  12. 12.
    A. Fantini, L. Perniola, M. Armand, J.-F. Nodin, V. Sousa, A. Persico, J. Cluzel, C. Jahan, S. Maitrejean, S. Lhostis, A. Roule, C. Dressler, G. Reimbold, B. De Salvo, P. Mazoyer, D. Bensahel, F. Boulanger, Comparative assessment of GST and GeTe materials for application to embedded phase-change memory devices, in IEEE International Memory Workshop. pp. 1–2, 10–14 May 2009Google Scholar
  13. 13.
    L. Perniola, V. Sousa, A. Fantini, E. Arbaoui, A. Bastard, M. Armand, A. Fargeix, C. Jahan, J.-F. Nodin, A. Persico, D. Blachier, A. Toffoli, S. Loubriat, E. Gourvest, G. Betti Beneventi, H. Feldis, S. Maitrejean, S. Lhostis, A. Roule, O. Cueto, G. Reimbold, L. Poupinet, T. Billon, B. De Salvo, D. Bensahel, P. Mazoyer, R. Annunziata, P. Zuliani, F. Boulanger, Electrical behavior of phase-change memory cells based on GeTe. IEEE Electron Device Lett. 31(5), 488–490 (May 2010)CrossRefGoogle Scholar
  14. 14.
    G. Betti Beneventi, E. Gourvest, A. Fantini, L. Perniola, V. Sousa, S. Maitrejean, J. C. Bastien, A. Bastard, A. Fargeix, B. Hyot, C. Jahan, J. F. Nodin, A. Persico, D. Blachier, A. Toffoli, S. Loubriat, A. Roule, S. Lhostis, H. Feldis, G. Reimbold, T. Billon, B. De Salvo, L. Larcher, P. Pavan, D. Bensahel, P. Mazoyer, R. Annunziata, F. Boulanger, On carbon doping to improve GeTe-based phase-change memory data retention at high temperature, IEEE International Memory Workshop (IMW). pp. 1–4, 16–19 May 2010Google Scholar
  15. 15.
    S. Lai, Current status of the phase change memory and its future, in IEDM Technical Digest. pp. 225–228, Dec 2003Google Scholar
  16. 16.
    S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y.-C. Chen, R. M. Shelby, M. Salinga, D. Krebs, S.-H. Chen, H.-L. Lung, C. H. Lam, Phase-change random access memory: a scalable technology, IBM. J. Res. Dev. 52(4-5), 465–479, (2008)CrossRefGoogle Scholar
  17. 17.
    G. Bruns, P. Merkelbach, C. Schlockermann, M. Salinga, M. Wuttig, T. D. Happ, J. B. Philipp, M. Kund, Nanosecond switching in GeTe phase change memory cells, Appl. Phys. Lett. 95(4), (2009)Google Scholar
  18. 18.
    G.Servalli, A 45 nm generation phase change memory technology, IEDM Technical Digest. pp. 113–116, 2009Google Scholar
  19. 19.
    J.H. Oh, J.H. Park, Y.S. Lim, H.S. Lim, Y.T. Oh, J.S. Kim, J.M. Shin, Y.J. Song, K.C. Ryoo, D.W. Lim, S.S. Park, J.I. Kim, J.H. Kim, J.Yu, F. Yeung, C.W. Jeong, J.H. Kong, D.H. Kang, G.H. Koh, G.T. Jeong, H.S. Jeong, K.Kinam, Full integration of highly manufacturable 512 Mb PRAM based on 90 nm Technology, in IEDM Technical Digest. p. 49–52, 2006Google Scholar
  20. 20.
    D. Ielmini, M. Boniardi, Common signature of many-body thermal excitation in structural relaxation and crystallization of chalcogenide glasses. Appl. Phys. Lett. 94(09), 091906 (2009)CrossRefGoogle Scholar
  21. 21.
    D. Ielmini, Y. Zhang, Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices. J. Appl. Phys. 102(5), 054517 (2007)CrossRefGoogle Scholar
  22. 22.
    G. Betti Beneventi, A. Calderoni, P. Fantini, L. Larcher, P. Pavan, Analytical model for low-frequency noise in amorphous chalcogenide-based phase-change memory devices. J. Appl. Phys. 106(5), 054506 (2009)CrossRefGoogle Scholar
  23. 23.
    T. Morikawa, K. Kurotsuchi, M. Kinoshita, N. Matsuzaki, Y. Matsui, Y. Fuiisaki, S. Hanzawa, A. Kotabe, M. Terao, H. Moriya, T. Iwasaki, M. Matsuoka, F. Nitta, M. Moniwa, T. Koga, N. Takaura, Doped in-Ge-Te phase change memory featuring stable operation and good data retention, in IEEE International Electron Devices Meeting. pp. 307–310, 10–12 Dec. 2007Google Scholar
  24. 24.
    B. Gleixner, F. Pellizzer, R. Bez, Reliability characterization of phase change Memory, in 10th Annual Non-volatile Memory Technology Symposium. pp. 7–11, 25–28 Oct. 2009Google Scholar
  25. 25.
    T. H. Jeong, M. R. Kim, H. Seo, J. W. Park and C. Yeon, Crystal structure and microstructure of nitrogen-doped Ge2Sb2Te5 Thin Film, Jpn. J Appl. Phys.39, 2775–2779, (2009)CrossRefGoogle Scholar
  26. 26.
    Y. Lai, B. Qiao, J. Feng, Y. Ling, L. Lai, Y. Lin, T. Tang, B. Cai, B. Chen, “Nitrogen-doped Ge2Sb2Te5 films for nonvolatile memory,” J. Electron. Mater. 34(2), 176–181, (2005)CrossRefGoogle Scholar
  27. 27.
    A.L. Lacaita, D.J. Wouters, Phase-change memories, Phys. Status solidi (a), 205(10), 2281–2297, Oct (2008)Google Scholar
  28. 28.
    A. Pirovano, F. Pellizzer, I. Tortorelli, A. Rigano, R. Harrigan, M. Magistretti, P. Petruzza, E. Varesi, A. Redaelli, D. Erbetta, T. Marangon, F. Bedeschi, R. Fackenthal, G. Atwood, R. Bez, Phase-change memory technology with self-aligned μtrench cell architecture for 90 nm node and beyond, Solid-State Electron. 52(9), 1467–1472, Sept (2008)Google Scholar
  29. 29.
    K. SangBum, Z. Yuan, J.P. McVittie, H. Jagannathan, Y. Nishi, H.-S.P. Wong, Integrating phase-change memory cell with Ge nanowire diode for crosspoint memory—experimental demonstration and analysis, IEEE Trans. Electron. Dev. 55(9), 2307–2313, Sept (2008)Google Scholar
  30. 30.
    S. Brown, R. Francis, J. Rose, Z. Vranesic, Field-Programmable Gate Arrays with Embedded Memories, (Kluwer Academic Publisher, 1992)Google Scholar
  31. 31.
    Executive Summary, Updated Edition, International Technology Roadmap for Semiconductors (2010).
  32. 32.
    V. Betz, J. Rose, A. Marquart, Architecture and CAD for Deep-Submicron FPGAs, (Kluwer Academic Publishers, New York, 1999) p. 264Google Scholar
  33. 33.
    J.H. Kyung, N. Chan, K. Sungraen, L. Ben, V. Hecht, B. Cronquist, A novel flash-based FPGA technology with deep trench isolation, IEEE Non-volatile Semiconductor Memory Workshop. pp. 32–33, 2007Google Scholar
  34. 34.
    K. J. Han, N. Chan, S. Kim B. Leung. V. Hecht, and B. Cronquist, A novel flash-based FPGA technology with deep trench isolation, IEEE Non-volatile Semiconductor Memory Workshop. pp. 32–33, 26–30 Aug 2007Google Scholar
  35. 35.
    N. Bruchon, L. Torres, G. Sassatelli, G. Cambon, New nonvolatile FPGA concept using magnetic tunneling junction, in IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures. pp. 6, 2–3 March 2006Google Scholar
  36. 36.
    J.Z. Sun, D.C. Ralph, Magnetorsistance and spin-transfer torque in magnetic tunnel junctions. J. Magn. Magn. Mater. 320(7), 1227–1237 (2008)CrossRefGoogle Scholar
  37. 37.
    Y. Guillemenet, L. Torres and G. Sassatelli, “Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories, IET. Comput. Digit. Tec. 4(3), 211–226, May (2010)Google Scholar
  38. 38.
    S. Onkaraiah, P.-E. Gaillardon, M. Reyboz, F. Clermidy, J.-M. Portal, M. Bocquet, C. Muller, Using OxRRAM memories for improving communications of reconfigurable FPGA architectures, in IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch). San Diego (CA), USA.08–09 June 2011Google Scholar
  39. 39.
    Y. Akasaka, T. Nishimura, Concept and basic technologies for 3D IC structure, in International Electron Devices Meeting. 32, 1986, pp. 488– 491Google Scholar
  40. 40.
    A. Rahman, J. Trezza, B. New, S. Trimberger, Die stacking technology for terabit Chip-to-Chip communications, in IEEE Custom Integrated Circuits Conference, CICC ‘06. pp. 587–590, 10–13 Sept 2006Google Scholar
  41. 41.
    D. Henry, S. Cheramy, J. Charbonnier, P. Chausse, M. Neyret, C. Brunet-Manquat, S. Verrun, N. Sillon, L. Bonnot, X. Gagnard, E. Saugier, 3D integration technology for set-top box application, in IEEE International Conference on 3D System Integration, 3DIC 2009. pp. 1–7, 28–30, Sept 2009Google Scholar
  42. 42.
    P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer, B. Previtali, C. Tabone, L. Clavelier, S. Michaud, A. Valentian, O. Thomas, O. Rozeau, P. Coudrain, C. Leyris, K. Romanjek, X. Garros, L. Sanchez, L. Baud, A. Roman, V. Carron, H. Grampeix, E. Augendre, A. Toffoli, F. Allain, P. Grosgeorges, V. Mazzochi, L. Tosti, F. Andrieu, J.-M. Hartmann, D. Lafond, S. Deleonibus, O. Faynot, GeOI and SOI 3D monolithic cell integrations for high density applications, in 2009 Symposium on VLSI Technology. pp. 166–167, 16–18 June 2009Google Scholar
  43. 43.
    P. Batude, M. Vinet, A. Pouydebasque, L. Clavelier, C. LeRoyer, C. Tabone, B. Previtali, L. Sanchez, L. Baud, A. Roman, V. Carron, F. Nemouchi, S. Pocas, C. Comboroure, V. Mazzocchi, H. Grampeix, F. Aussenac, S. Deleonibus, Enabling 3D monolithic integration. ECS J. 6, 47 (2008)CrossRefGoogle Scholar
  44. 44.
    Y.-H. Son, J.-W. Lee; P. Kang, M.-G. Kang, J. B. Kim, S. H. Lee, Y.-P. Kim, I. S. Jung, B. C. Lee; S. Y. Choi; U-I. Chung, J. T. Moon, B.-I. Ryu, “Laser-induced Epitaxial Growth (LEG) Technology for High Density 3D Stacked Memory with High Productivity, in IEEE symposium on VLSI technology. pp. 80–81, 12–14 June 2007Google Scholar
  45. 45.
    S. E. Steen, D. LaTulipe, A.W. Topol, D.J. Frank, K. Belote, D. Posillico, Overlay as the key to drive wafer scale 3D integration, Microelectron. Eng. 84(5–8), 1412–1415, May–August 2007Google Scholar
  46. 46.
    P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer, B. Previtali, C. Tabone, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, A. Toffoli, F. Allain, V. Mazzocchi, D. Lafond, N. Bouzaida, O. Thomas, O. Cueto, A. Amara1, S. Deleonibus, O. Faynot, Advances in 3D CMOS sequential integration, in IEEE International Device Meeting. 2009Google Scholar
  47. 47.
    M. Ieong, B. Doris, J. Kedzierski, K. Rim, M. Yang, Silicon device scaling to sub-10-nm regime, Science, 306(5704), 2057–2060, (2004)Google Scholar
  48. 48.
    J. Hahm, C.M. Lieber, Direct ultrasensitive electrical detection of DNA and DNA sequence variations using nanowire nanosensors, Nano Lett.4, 51–54, (2004)Google Scholar
  49. 49.
    T. Ernst, E. Bernard, C. Dupre, A. Hubert, S. Becu, B. Guillaumot, O. Rozeau, O. Thomas, P. Coronel, J.-M. Hartmann, C. Vizioz, N. Vulliet, O. Faynot, T. Skotnicki, S. Deleonibus, 3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics, IEEE International Conference on Integrated Circuit Design and Technology and Tutorial,ICICDT 2008. pp. 265–268, 2–4 June 2008Google Scholar
  50. 50.
    T. Ernst T. Ernst, L. Duraffourg, C. Dupré, E. Bernard, P. Andreucci, S. Bécu, E. Ollier, A. Hubert, C. Halté, J. Buckley, O. Thomas, G. Delapierre, S. Deleonibus, B. de Salvo, P. Robert, O. Faynot, Novel Si-based nanowire devices: will they serve ultimate MOSFETs scaling or ultimate hybrid integration?, in IEEE International Electron Devices Meeting. 2008Google Scholar
  51. 51.
    A.-L. Bavencove, G. Tourbot, E. Pougeoise, J. Garcia, P. Gilet, F. Levy, B. André, G. Feuillet, B. Gayral, B. Daudin, Le S. Dang, GaN-based nanowires: from nanometric-scale characterization to light emitting diodes, Physica Status Solidi (a), 207(6), 1425–1427, (2010)Google Scholar
  52. 52.
    Y. Cui, Z. Zhong, D. Wang, W. U. Wang, C.M. Lieber, High performance silicon nanowire field effect transistors, Nano Lett.3, 149–152, (2003)Google Scholar
  53. 53.
    J. Goldberger, A. I. Hochbaum, R. Fan, P. Yang, Silicon vertically integrated nanowire field effect transistors, Nano Lett. 6(5), 973–977, (2006)CrossRefGoogle Scholar
  54. 54.
    V. Schmidt, H. Riel, S. Senz, S. Karg, W. Riess, U. Gösele, Realization of a silicon nanowire vertical surround-gate field-effect transistor. Small 2(1), 85–88 (2006)CrossRefGoogle Scholar
  55. 55.
    V.T. Renard, M. Jublot, P. Gergaud, P. Cherns, D. Rouchon, A. Chabli, V. Jousseaume, Catalyst preparation for CMOS-compatible silicon nanowire synthesis. Nat. Nanotechnol. 4, 654–657 (2009)CrossRefGoogle Scholar
  56. 56.
    ATLAS User’s Manual, SILVACO, 2008Google Scholar
  57. 57.
    C. A. Moritz, T. Wang, Latching on the wire and pipelining in nanoscale designs, 3rd Workshop on Non-silicon Computation (NSC-3). June 2004Google Scholar
  58. 58.
    T. Wang, P. Narayanan, C. A. Moritz, Combining two-level logic families in grid-based nanoscale fabrics, in IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). October 2007Google Scholar
  59. 59.
    P. Vijayakumar, P. Narayanan, I. Koren, C. M. Krishna, C. A. Moritz, Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics, in IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). June 2011Google Scholar

Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Pierre-Emmanuel Gaillardon
    • 1
  • Ian O’Connor
    • 2
  • Fabien Clermidy
    • 3
  1. 1.INF 339 (Bâtiment INF)EPFL IC ISIM LSI1LausanneSwitzerland
  2. 2.Bâtiment F7INL, Site Ecole Centrale de LyonEcullyFrance
  3. 3.CEA-LETIMINATECGrenobleFrance

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