Abstract
The performance of data-intensive applications is often limited not only by the computational power of current computers but also by the performance gap between the CPU and the main system memory. Data prefetch mechanisms mask this latency by moving data closer to the CPU automatically. These methods rely on predicting future memory addresses; however, they are not suited for applications with random memory access patterns. Preexecution is a prefetch method which executes a slice of the original algorithm in parallel with the main thread to calculate memory addresses and issue loads early. In this paper we propose a lightweight software preexecution strategy for data parallel applications that accelerates the main working thread with an adaptive preexecution helper thread acting as a perfect predictor and consuming cache misses. With automatic parameter tuning the helper thread adapts to the application and system it is executed on. This method was able to achieve an average speedup of 10–30% in a real-life data parallel application.
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Acknowledgment
This project is supported by the New Hungary Development Plan (Project ID: TÁMOP-4.2.1/B-09/1/KMR-2010-0002).
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Dudás, Á., Juhász, S. (2013). Reconfigurable Preexecution in Data Parallel Applications on Multicore Systems. In: Ao, SI., Gelman, L. (eds) Electrical Engineering and Intelligent Systems. Lecture Notes in Electrical Engineering, vol 130. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-2317-1_3
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DOI: https://doi.org/10.1007/978-1-4614-2317-1_3
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