Abstract
The push towards wider bandwidths in baseband filter applications calls for operational transconductance amplifiers (OTAs) with progressively better linearity at higher frequencies. In this chapter, an architectural solution is described that can be applied to diverse circuit-level OTA configurations. Effective linearization over a wide frequency range demands a mechanism to correct for high-frequency effects and process variations. Accordingly, digital programmability to ensure high linearity and compatibility with modern CMOS technologies is discussed. The linearization technique utilizes two matched OTAs to cancel harmonic distortion components, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors.
This chapter includes portions reprinted with permission, from “Attenuation-predistortion linearization of CMOS OTAs with digital correction of process variations in OTA-C filter applications,” M. Mobarak, M. Onabajo, J. Silva-Martinez, and E. Sánchez-Sinencio, IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 351–367, Feb. 2010, © 2010 IEEE.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
V. Saari, M. Kaltiokallio, S. Lindfors, J. Ryynänen, K.A.I. Halonen, A 240 MHz low-pass filter with variable gain in 65-nm CMOS for a UWB radio receiver. IEEE Trans. Circuits Syst. Regul. Pap. 56(7), 1488–1499 (2009)
M. Gambhir, V. Dhanasekaran, J. Silva-Martinez, E. Sánchez-Sinencio, A low power 1.3 GHz dual-path current mode Gm-C filter, in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sept 2008, pp. 703–706
R. Schoofs, M.S.J. Steyaert, W.M.C. Sansen, A design-optimized continuous-time delta-sigma ADC for WLAN applications. IEEE Trans. Circuits Syst. Regul. Pap. 54(1), 209–217 (2007)
D. Healy, Analog-to-Information (A-to-I) Receiver Development Program, BAA 08-03 Announcement, Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO), Nov 2007
J.C. Rudell, O.E. Erdogan, D.G. Yee, R. Brockenbrough, C.S.G. Conroy, B. Kim, A 5th-order continuous-time harmonic-rejection GmC filter with in situ calibration for use in transmitter applications, in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, Feb 2005, pp 322–323
A. Lewinski, J. Silva-Martinez, A high-frequency transconductor using a robust nonlinearity cancellation. IEEE Trans. Circuits Syst. Express Briefs 53(9), 896–900 (2006)
E.A.M. Klumperink, B. Nauta, Systematic comparison of HF CMOS transconductors. IEEE Trans. Circuits Syst. Express Briefs 50(10), 728–741 (2003)
S. D’Amico, M. Conta, A. Baschirotto, A 4.1 mW 10 MHz fourth-order source-follower-based continuous-time filter with 79 dB DR. IEEE J. Solid-State Circuits 41(12), 2713–2719 (2006)
T.Y. Lo, C.-C. Hung, A 40 MHz double differential-pair CMOS OTA with −60 dB IM3. IEEE Trans. Circuits Syst. Regul. Pap. 55(1), 258–265 (2008)
J. Chen, E. Sánchez-Sinencio, J. Silva-Martinez, Frequency-dependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters. IEEE Trans. Circuits Syst. Regul. Pap. 53(3), 499–510 (2006)
W. Huang, E. Sánchez-Sinencio, Robust highly linear high-frequency CMOS OTA with IM3 below −70 dB at 26 MHz. IEEE Trans. Circuits Syst. Regul. Pap. 53(7), 1433–1447 (2006)
D. Yongwang, R. Harjani, A +18 dBm IIP3 LNA in 0.35 μm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, Feb 2001, pp. 162–163
M. Mobarak, M. Onabajo, J. Silva-Martinez, E. Sánchez-Sinencio, Attenuation- predistortion linearization of CMOS OTAs with digital correction of process variations in OTA-C filter applications. IEEE J. Solid-State Circuits 45(2), 351–367 (2010)
R. Chawla, F. Adil, G. Serrano, P.E. Hasler, Programmable Gm-C filters using floating-gate operational transconductance amplifiers. IEEE Trans. Circuits Syst. Regul. Pap. 54(3), 481–491 (2007)
S. Maas, Nonlinear Microwave and RF Circuits (Artech House, Boston, 2003)
E. Rodriguez-Villegas, H. Barnes, Solution to trapped charge in FGMOS transistors. Electron. Lett. 39(19), 1416–1417 (2003)
A.P. Nedungadi, R.L. Geiger, High-frequency voltage-controlled continuous time lowpass filter using linearized CMOS integrators. Electron. Lett. 22, 729–731 (1986)
D. Kaczman, M. Shah, M. Alam, M. Rachedine, D. Cashen, L. Han, A. Raghavan, A single-chip 10-band WCDMA/HSDPA 4-band GSM/EDGE SAW-less CMOS receiver with DigRF 3G interface and +90 dBm IIP2. IEEE J. Solid-State Circuits 44(3), 718–739 (2009)
H. Darabi, J. Chiu, S. Khorram, H.J. Kim, Z. Zhou, H.-M. Chien, B. Ibrahim, E. Geronaga, L.H. Tran, A. Rofougaran, A dual-mode 802.11b/Bluetooth radio in 0.35 μm CMOS. IEEE J. Solid-State Circuits 40(3), 698–706 (2005)
I. Vassiliou, K. Vavelidis, T. Georgantas, S. Plevridis, N. Haralabidis, G. Kamoulakos, C. Kapnistis, S. Kavadias, Y. Kokolakis, P. Merakos, J.C. Rudell, A. Yamanaka, S. Bouras, I. Bouras, A single-chip digitally calibrated 5.15–5.825 GHz 0.18 μm CMOS transceiver for 802.11a wireless LAN. IEEE J. Solid-State Circuits 38(12), 2221–2231 (2003)
Y.-H. Hsieh, W.-Y. Hu, S.-M. Lin, C.-L. Chen, W.-K. Li, S.-J. Chen, D.J. Chen, An auto-I/Q calibrated CMOS transceiver for 802.11g. IEEE J. Solid-State Circuits 40(11), 2187–2192 (2005)
A. Valdes-Garcia, R. Venkatasubramanian, R. Srinivasan, J. Silva-Martinez, E. Sánchez-Sinencio, A CMOS RF RMS detector for built-in testing of wireless transceivers, in Proceedings of IEEE VLSI Test Symposium, May 2005, pp. 249–254
A. Valdes-Garcia, R. Venkatasubramanian, J. Silva-Martinez, E. Sánchez-Sinencio, A broadband CMOS amplitude detector for on-chip RF measurements. IEEE Trans. Instrum. Meas. 57(7), 1470–1477 (2008)
G. Bollati, S. Marchese, M. Demicheli, R. Castello, An eighth-order CMOS low-pass filter with 30–120 MHz tuning range and programmable boost. IEEE J. Solid-State Circuits 36(7), 1056–1066 (2001)
A. Otin, S. Celma, C. Aldea, A 40–200 MHz programmable 4th-order Gm-C filter with auto-tuning system, in Proceedings of 33rd European Solid-State Circuits Conference (ESSCIRC), Sept 2007, pp. 214–217
S. Dosho, T. Morie, H. Fujiyama, A 200 MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25 μm CMOS process. IEEE J. Solid-State Circuits 37(5), 559–565 (2002)
S. Pavan, T. Laxminidhi, A 70–500 MHz programmable CMOS filter compensated for MOS nonquasistatic effects, in Proceedings of 32nd European Solid-State Circuits Conference (ESSCIRC), Sept 2006, pp. 328–331
K. Kwon, H.-T. Kim, K. Lee, A 50–300 MHz highly linear and low-noise CMOS Gm-C filter adopting multiple gated transistors for digital TV tuner ICs. IEEE Trans. Microwave Theory Tech. 57(2), 306–313 (2009)
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer Science+Business Media New York
About this chapter
Cite this chapter
Onabajo, M., Silva-Martinez, J. (2012). High-Linearity Transconductance Amplifiers with Digital Correction Capability. In: Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-2296-9_3
Download citation
DOI: https://doi.org/10.1007/978-1-4614-2296-9_3
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4614-2295-2
Online ISBN: 978-1-4614-2296-9
eBook Packages: EngineeringEngineering (R0)