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System-Level Design for Robustness

  • Pooyan Sakian
  • Reza Mahmoudi
  • Arthur van Roermund
Chapter
  • 946 Downloads
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

The increasing demand for compactness and speed of digital circuits and the necessity of integration of the digital backend electronics with radio frequency frontends, calls for exploiting deep submicron technologies in RF circuit design. However, scaling into the deep submicron regime, mainly in CMOS technologies, accentuates the effect of process spread and mismatch on the fabrication yield [10]. Furthermore, design for manufacturability requires all manufacturing and process variations to be considered in the design procedure. Statistical circuit-level methods based on modeling data provided by fabrication foundries, e.g. Monte Carlo, are extensively used to evaluate the effect of process spread and are utilized by simulation tools to design circuits with the desired performance over the specified range of process variation [8]. However, most of these statistical methods are based on random variation of design variables which need long simulation times for large-scale circuits, like a full receiver. Furthermore, as the size and complexity of designs is increased, less insight is obtained from these random statistical methods.

Keywords

Phase Noise Power Coefficient Total Noise Order Sensitivity Front Stage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 8.
    Meehan MD, Purviance J (1993) Yield and reliability in microwave circuit and system design. Artech House, BostonGoogle Scholar
  2. 10.
    Pang L-T, Qian K, Spanos CJ, Nikolic B (2009) Measurement and analysis of variability in 45 nm strained-Si CMOS technology. IEEE J Solid State Circuits 44(8):2233–2243CrossRefGoogle Scholar
  3. 12.
    Sheng W, Emira A, Sanchez-Sinencio E (2006) CMOS RF receiver system design: a systematic approach. IEEE Trans Circuits Syst-I: Reg Pap 53(5):1023–1034Google Scholar
  4. 13.
    Baltus P (2004) Minimum power design of RF front ends. PhD Dissertation, Eindhoven University of TechnologyGoogle Scholar
  5. 14.
    El-Nozahi M, Sanchez-Sinencio E, Entesari K (2009) Power-aware multiband–multistandard CMOS receiver system-level budgeting. IEEE Trans Circuits Syst II: Exp Brief 56(7):570–574CrossRefGoogle Scholar
  6. 15.
    Part 15.3: wireless medium access control (MAC) and physical layer (PHY) specifications for high rate wireless personal area networks (WPANs): amendment 2: millimeter-wave based alternative physical layer extension. IEEE 802.15.3c, Oct 2009Google Scholar
  7. 16.
    Janssen E, Mahmoudi R, van der Heijden E, Sakian P, de Graauw A, Pijper R, van Roermund A (2010) Fully balanced 60 GHz LNA with 37% bandwidth, 3.8 dB NF, 10 dB gain and constant group delay over 6 GHz bandwidth. 10th topical meeting on silicon monolithic integrated circuits in RF systems, Jan 2010Google Scholar
  8. 17.
    Sakian P, Mahmoudi R, van der Heijden E, de Graauw A, van Roermund A (2011) Wideband cancellation of second order intermodulation distortions in a 60 GHz zero-IF mixer. 11th topical meeting on silicon monolithic integrated circuits in RF systems, Jan 2011Google Scholar
  9. 18.
    Tomkins A, Aroca RA, Yamamoto T, Nicolson ST, Doi Y, Voinigescu SP (2009) A zero-IF 60 GHz 65 nm CMOS transceiver with direct BPSK modulation demonstrating up to 6 Gb/s data rate over a 2 m wireless link. IEEE J Solid State Circuits 44(8):2085–2099CrossRefGoogle Scholar
  10. 19.
    Marcu C, Chowdhury D, Thakkar C, Park J-D, Kong L-K, Tabesh M, Wang Y, Afshar B, Gupta A, Arbabian A, Gambini S, Zamani R, Alon E, Niknejad AM (2009) A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry. IEEE J Solid State Circuits 44(12):3434–3447CrossRefGoogle Scholar
  11. 20.
    Alpman E, Lakdawala H, Carley LR, Soumyanath K (2009) A 1.1 V 50 mW 2.5 GS/s 7b time-interleaved C-2C SAR ADC in 45 nm LP digital CMOS. IEEE international solid state circuits conference, Feb 2009Google Scholar
  12. 21.
    Deng W, Mahmoudi R, Harpe P, van Roermund A (2008) An alternative design flow for receiver optimization through a trade-off between RF and ADC. IEEE radio wireless symposium, Jan 2008Google Scholar
  13. 22.
    Yang J, Lin Naing T, Brodersen RW (2010) A 1 GS/s 6 Bit 6.7 mW successive approximation ADC using asynchronous processing. IEEE J Solid State Circuits 45(8):1469–1478CrossRefGoogle Scholar
  14. 101.
    Verbruggen B, Craninckx J, Kuijk M, Wambacq P, Van der Plas G (2010) A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. IEEE international solid-state circuits conference digest of technical papers, Feb 2010, pp 296–298Google Scholar

Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Pooyan Sakian
    • 1
  • Reza Mahmoudi
    • 1
  • Arthur van Roermund
    • 1
  1. 1.Eindhoven University of TechnologyEindhovenThe Netherlands

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