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Hardware Architecture Assist for Critical Components

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Video Surveillance for Sensor Platforms

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 114))

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Abstract

Despite the advancements in both software and hardware, the majority of accurate image processing algorithms still contain some computational parts. These critical sections are viewed as bottleneck especially when real-time response is desired. Specialized hardware solutions are developed to accelerate critical low-level such operations. In this chapter, two hardware architectures are presented to complement image processing algorithms discussed in previous chapters. The first is a fast and compact ASIC architecture for hysteresis thresholding and object feature extraction. The second is an efficient hardware implementation for image decomposition based on Discrete Wavelet Transform. Both architectures exhibit higher performance than their software counterpart and hence help in alleviating the burden off the processing tasks.

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Authors and Affiliations

  1. University of Louisiana at Lafayette, Lafayette, USA

    Mayssaa Al Najjar & Magdy Bayoumi

  2. Lebanese International University, Beirut, Lebanon

    Milad Ghantous

Authors
  1. Mayssaa Al Najjar
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  2. Milad Ghantous
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  3. Magdy Bayoumi
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Al Najjar, M., Ghantous, M., Bayoumi, M. (2014). Hardware Architecture Assist for Critical Components. In: Video Surveillance for Sensor Platforms. Lecture Notes in Electrical Engineering, vol 114. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1857-3_8

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  • DOI: https://doi.org/10.1007/978-1-4614-1857-3_8

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-1856-6

  • Online ISBN: 978-1-4614-1857-3

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