Reconfigurable Memories



Over the past years, the growing performance gap between large memories and computational logic fueled an increased usage of complex memory hierarchies. The main goal of such hierarchies is to provide data and instructions to the processing elements with maximum efficiency, both in terms of latency and energy consumption. The importance of using an efficient memory hierarchy places it as a critical component also in embedded systems, where one often faces strict performance and power constraints.In Chap.2, we have discussed that, since different applications have different requirements and behaviors, the optimal processing structure for each one is also different. This same property applies when one considers memories: a memory hierarchy specifically tailored for a given use pattern is able to provide optimum throughput with reduced energy consumption. This same specific structure, however, may perform poorly when used directly with other applications, without any adaptation. Hence, just as reconfigurable architectures adapt themselves to better fit each application, reconfigurable memories should shape to the requirements of the application under execution. In this chapter we present the basic concepts and technology tradeoffs involved in memory hierarchies and discuss possible approaches to provide adaptability for such structures.


Block Size Cache Size Memory Hierarchy Cache Memory Design Space Exploration 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Albonesi, D.: Selective cache ways: on-demand cache resource allocation. In: Proceedings of the 32nd Annual International Symposium on Microarchitecture, 1999. MICRO-32. pp. 248–259 (1999). doi:10.1109/MICRO.1999.809463Google Scholar
  2. 2.
    Austin, T., Larson, E., Ernst, D.: SimpleScalar: an infrastructure for computer system modeling. Computer 35(2), 59–67 (2002). doi:10.1109/2.982917CrossRefGoogle Scholar
  3. 3.
    Banakar, R., Steinke, S., Lee, B.S., Balakrishnan, M., Marwedel, P.: Scratchpad memory: design alternative for cache on-chip memory in embedded systems. In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES ’02, pp. 73–78. ACM, New York (2002). doi:10.1145/774789.774805.
  4. 4.
    Beck, A.C.S., Rutzig, M.B., Gaydadjiev, G., Carro, L.: Transparent reconfigurable acceleration for heterogeneous embedded applications. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’08, pp. 1208–1213. ACM, New York (2008). doi:10.1145/1403375.1403669.
  5. 5.
    Berticelli Lo, T., Beck, A., Rutzig, M., Carro, L.: A low-energy approach for context memory in reconfigurable systems. In: IEEE International Symposium on Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 pp. 1–8. IEEE, Piscataway (2010)Google Scholar
  6. 6.
    Girão, G., Santini, T., Wagner, F.: Dynamic clustering for distinct parallel programming models on NoC-based MPSoCs. In: Proceedings of the 4th International Workshop on Network on Chip Architectures, NoCArc ’11, pp. 63–68. ACM, New York 2011. doi:10.1145/2076501.2076514.
  7. 7.
    Givargis, T., Vahid, F.: Tuning of cache ways and voltage for low-energy embedded system platforms. Des. Autom. Embed. Syst. 7, 35–51 (2002)MATHCrossRefGoogle Scholar
  8. 8.
    Hennessy, J.L., Patterson, D.A.: Computer Architecture – A Quantitative Approach, 5th edn. Morgan Kaufmann, Amsterdam/Boston (2012)MATHGoogle Scholar
  9. 9.
    Herrero, E., González, J., Canal, R.: Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors. In: Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA ’10, pp. 419–428. ACM, New York (2010). doi:
  10. 10.
    Huh, J., Kim, C., Shafi, H., Zhang, L., Burger, D., Keckler, S.W.: A NUCA substrate for flexible CMP cache sharing. In: Proceedings of the 19th Annual International Conference on Supercomputing, ICS ’05, pp. 31–40. ACM, New York (2005). doi:
  11. 11.
    Mai, K., Paaske, T., Jayasena, N., Ho, R., Dally, W., Horowitz, M.: Smart Memories: a modular reconfigurable architecture. In: Proceedings of the 27th International Symposium on Computer Architecture, 2000. pp. 161–171. ACM, New York (2000)Google Scholar
  12. 12.
    Muralimanohar, N., Balasubramonian, R., Jouppi, N.P.: CACTI 6.0: A tool to model large caches. Tech. rep., HP (2009).
  13. 13.
    Patterson, D.A., Hennessy, J.L.: Computer Organization and Design – The Hardware/Software Interface, Revised 4th edn. The Morgan Kaufmann Series in Computer Architecture and Design. Morgan Kaufmann, Burlington, MA, USA (2012)Google Scholar
  14. 14.
    Qureshi, M., Thompson, D., Patt, Y.: The V-Way cache: demand-based associativity via global replacement. In: Proceedings of the 32nd International Symposium on Computer Architecture, 2005. ISCA ’05. pp. 544–555. (2005). doi:10.1109/ISCA.2005. 52Google Scholar
  15. 15.
    Rauber, T., Rünger, G., Rauber, T., Rnger, G.: Parallel programming models. In: Parallel Programming, pp. 93–149. Springer, Berlin/Heidelberg (2010)Google Scholar
  16. 16.
    Weinhardt, M., Luk, W.: Memory access optimisation for reconfigurable systems. Computers and Digital Techniques, IEE Proc. Comput. Digit. Tech. 148(3), 105–112 (2001). doi:10.1049/ip-cdt:20010514Google Scholar
  17. 17.
    Xu, B., Albonesi, D.H.: Runtime reconfiguration techniques for efficient general-purpose computation. IEEE Des. Test 17, 42–52 (2000). doi:10.1109/54.825676. Google Scholar
  18. 18.
    Zhang, C., Vahid, F., Najjar, W.: A highly configurable cache architecture for embedded systems. In: Proceedings of the 30th Annual International Symposium on Computer Architecture, 2003. pp. 136–146 (2003). doi:10.1109/ISCA.2003.1206995 Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Instituto de InformáticaUniversidade Federal do Rio Grande do SulPorto AlegreBrazil

Personalised recommendations