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Reconfigurable Memories

Chapter

Abstract

Over the past years, the growing performance gap between large memories and computational logic fueled an increased usage of complex memory hierarchies. The main goal of such hierarchies is to provide data and instructions to the processing elements with maximum efficiency, both in terms of latency and energy consumption. The importance of using an efficient memory hierarchy places it as a critical component also in embedded systems, where one often faces strict performance and power constraints.In Chap.2, we have discussed that, since different applications have different requirements and behaviors, the optimal processing structure for each one is also different. This same property applies when one considers memories: a memory hierarchy specifically tailored for a given use pattern is able to provide optimum throughput with reduced energy consumption. This same specific structure, however, may perform poorly when used directly with other applications, without any adaptation. Hence, just as reconfigurable architectures adapt themselves to better fit each application, reconfigurable memories should shape to the requirements of the application under execution. In this chapter we present the basic concepts and technology tradeoffs involved in memory hierarchies and discuss possible approaches to provide adaptability for such structures.

Keywords

Block Size Cache Size Memory Hierarchy Cache Memory Design Space Exploration 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Instituto de InformáticaUniversidade Federal do Rio Grande do SulPorto AlegreBrazil

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