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Adaptable Embedded Systems pp 41–94Cite as

Reconfigurable Systems

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Abstract

This chapter aims to explain the basics of reconfigurable systems. It starts with a basic explanation on how these architectures work, their main principles, and where the gains come from. After that, this chapter gives an overview on the classification of reconfigurable systems, which includes granularity, instruction types and coupling. Following this discussion, several and different examples of architectures that have been used both in the academy and in the industry are shown. They are presented according to the classification studied in the previous sections of this same chapter. Finally, a brief overview on recent dataflow machines is given, as their structure is very similar to some of the reviewed reconfigurable systems.

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References

  1. Arnold, J.M., et al.: The splash 2 processor and applications. In: International Conference on Computer Design. CS Press, Mun̈chen (1993)

    Google Scholar 

  2. Athanas, P.M., Silverman, H.F.: Processor reconfiguration through instruction-set metamorphosis. Computer 26(3), 11–18 (1993). doi:http://dx.doi.org/10.1109/2.204677

    Google Scholar 

  3. Barat, F., Lauwereins, R.: Reconfigurable instruction set processors: a survey. In: RSP ’00: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), p. 168. IEEE Computer Society, Washington, DC (2000)

    Google Scholar 

  4. Barua, R., Lee, W., Amarasinghe, S., Agarwal, A.: Maps: a compiler-managed memory system for raw machines. In: Proceedings of the 26th International Symposium on Computer Architecture, pp. 4–15. IEEE Computer Society, Los Alamitos (1998)

    Google Scholar 

  5. Barua, R., Lee, W., Amarasinghe, S., Agarwal, A.: Memory bank disambiguation using modulo unrolling for raw machines. In: Proceedings of the ACM/IEEE Fifth Int’l Conference on High Performance Computing(HIPC) (1998)

    Google Scholar 

  6. Baumgarte, V., Ehlers, G., May, F., Nückel, A., Vorbach, M., Weinhardt, M.: Pact xpp—a self-reconfigurable data processing architecture. J. Supercomput. 26(2), 167–184 (2003). doi:http://dx.doi.org/10.1023/A:1024499601571

    Google Scholar 

  7. Becker, J., Pionteck, T., Glesner, M.: DReAM: ADynamicallyReconfigurable architecture for future mobile communication applications. In: Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. Lecture Notes in Computer Science, vol. 1896, pp. 312–321. Springer Berlin/Heidelberg (2000). http://www.springerlink.com/content/3kvjdm6qxf9k7xt5/

  8. Bittner Jr. R., Athanas, P.M., Musgrove, M.D.: Colt: an experiment in wormhole run-time reconfiguration. In: High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, pp. 187–194 (1996)

    Google Scholar 

  9. Callahan, T., Hauser, J., Wawrzynek, J.: The garp architecture and c compiler. Computer 33(4), 62–69 (2000). doi:10.1109/2.839323

    Article  Google Scholar 

  10. Cardoso, J.M., Weinhardt, M.: Xpp-vc: A c compiler with temporal partitioning for the pact-xpp architecture. In: Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. Lecture Notes in Computer Science, vol. 2438, pp. 207–226. Springer, Berlin/Heidelberg (2002). http://www.springerlink.com/content/2rwnvdfwv79wev9u/

  11. Cardoso, J.M.P., Weinhardt, M.: Fast and guaranteed c compilation onto the PACT-XPP reconfigurable computing platform. In: FCCM ’02: Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p. 291. IEEE Computer Society, Washington, DC (2002)

    Google Scholar 

  12. Carrillo, J.E., Chow, P.: The effect of reconfigurable units in superscalar processors. In: FPGA ’01: Proceedings of the 2001 ACM/SIGDA Ninth International Symposium on Field programmable Gate Arrays, pp. 141–150. ACM, New York (2001). doi:http://doi.acm.org/10.1145/360276.360328

  13. Chang, P.P., Mahlke, S.A., Chen, W.Y., Warter, N.J., Hwu, W.m.W.: Impact: an architectural framework for multiple-instruction-issue processors. SIGARCH Comput. Archit. News 19(3), 266–275 (1991). doi:http://doi.acm.org/10.1145/115953.115979

  14. Chou, Y., Pillai, P., Schmit, H., Shen, J.P.: Piperench implementation of the instruction path coprocessor. In: MICRO 33: Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, pp. 147–158. ACM, New York (2000). doi:http://doi.acm.org/10.1145/360128.360144

  15. Clark, N., Kudlur, M., Park, H., Mahlke, S., Flautner, K.: Application-specific processing on a general-purpose core via transparent instruction set customization. In: MICRO 37: Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 30–40. IEEE Computer Society, Washington, DC (2004). doi:http://dx.doi.org/10.1109/MICRO.2004.5

  16. Compton, K., Hauck, S.: Reconfigurable computing: a survey of systems and software. ACM Comput. Surv. 34(2), 171–210 (2002). doi:http://doi.acm.org/10.1145/508352.508353

  17. Cronquist, D.C., Fisher, C., Figueroa, M., Franklin, P., Ebeling, C.: Architecture design of reconfigurable pipelined datapaths. In: ARVLSI ’99: Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI, p. 23. IEEE Computer Society, Washington, DC (1999)

    Google Scholar 

  18. Cronquist, D.C., Franklin, P., Berg, S.G., Ebeling, C.: Specifying and compiling applications for rapid. In: FCCM ’98: Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p. 116. IEEE Computer Society, Washington, DC (1998)

    Google Scholar 

  19. David, H.S., Whelihan, D., Tsai, A., Moe, M., Levine, B., Taylor, R.R.: Piperench: A virtualized programmable datapath in 0.18 micron technology. In: Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 63–66. IEEE Computer Society, Los Alamitos (2002)

    Google Scholar 

  20. DeHon, A.: Dpga utilization and application. In: FPGA ’96: Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays, pp. 115–121. ACM, New York (1996). doi:http://doi.acm.org/10.1145/228370.228387

  21. Ebeling, C., Cronquist, D.C., Franklin, P.: Rapid – reconfigurable pipelined datapath. In: FPL ’96: Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, pp. 126–135. Springer, London (1996)

    Google Scholar 

  22. Gebhart, M., Maher, B.A., Coons, K.E., Diamond, J., Gratz, P., Marino, M., Ranganathan, N., Robatmili, B., Smith, A., Burrill, J., Keckler, S.W., Burger, D., McKinley, K.S.: An evaluation of the trips computer system. In: ASPLOS ’09: Proceeding of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 1–12. ACM, New York (2009). doi:http://doi.acm.org/10.1145/1508244.1508246

  23. Goldstein, S.C., Schmit, H., Budiu, M., Cadambi, S., Moe, M., Taylor, R.R.: Piperench: a reconfigurable architecture and compiler. Computer 33(4), 70–77 (2000). doi:http://dx.doi.org/10.1109/2.839324

    Google Scholar 

  24. Goldstein, S.C., Schmit, H., Moe, M., Budiu, M., Cadambi, S., Taylor, R.R., Laufer, R.: Piperench: a co/processor for streaming multimedia acceleration. In: ISCA ’99: Proceedings of the 26th Annual International Symposium on Computer Architecture, pp. 28–39. IEEE Computer Society, Washington, DC (1999). doi:http://doi.acm.org/10.1145/300979.300982

  25. Hartenstein, R.: Coarse grain reconfigurable architecture (embedded tutorial). In: ASP-DAC ’01: Proceedings of the 2001 Conference on Asia South Pacific Design Automation, pp. 564–570. ACM, New York (2001). doi:http://doi.acm.org/10.1145/370155.370535

  26. Hartenstein, R., Herz, M., Hoffmann, T., Nageldinger, U.: Kressarray xplorer: a new cad environment to optimize reconfigurable datapath array. In: ASP-DAC ’00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference, pp. 163–168. ACM, New York (2000). doi:http://doi.acm.org/10.1145/368434.368597

  27. Hauck, S., Fry, T.W., Hosler, M.M., Kao, J.P.: The chimaera reconfigurable functional unit. In: FCCM ’97: Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p. 87. IEEE Computer Society, Washington, DC (1997)

    Google Scholar 

  28. Hauck, S., Fry, T.W., Hosler, M.M., Kao, J.P.: The chimaera reconfigurable functional unit. IEEE Trans. Very Large Scale Integr. Syst. 12(2), 206–217 (2004). doi:http://dx.doi.org/10.1109/TVLSI.2003.821545

    Google Scholar 

  29. Hauser, J.R., Wawrzynek, J.: Garp: a mips processor with a reconfigurable coprocessor. In: FCCM ’97: Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p. 12. IEEE Computer Society, Washington, DC (1997)

    Google Scholar 

  30. Heysters, P., Smit, G., Molenkamp, E.: A flexible and energy-efficient coarse-grained reconfigurable architecture for mobile systems. J. Supercomput. 26(3), 283–308 (2003). doi:http://doi:dx.doi.org/10.1023/A:1025699015398

    Google Scholar 

  31. Hwu, W.M.W., Mahlke, S.A., Chen, W.Y., Chang, P.P., Warter, N.J., Bringmann, R.A., Quellette, R.G., Hank, R.E., Kiyohara, T., Haab, G.E., Holm, J.G., Lavery, D.M.: The superblock: an effective technique for VLIW and superscalar compilation. The Journal of Supercomputing 7, pp. 229–248 Kluwer Academic Publishers Hingham, MA, USA (1993). http://dx.doi.org/10.1007/BF01205185

  32. Jain, M.K., Balakrishnan, M., Kumar, A.: Asip design methodologies: Survey and issues. In: VLSID ’01: Proceedings of the The 14th International Conference on VLSI Design (VLSID ’01), p. 76. IEEE Computer Society, Washington, DC (2001)

    Google Scholar 

  33. Kastrup, B., Bink, A., Hoogerbrugge, J.: Concise: A compiler-driven cpld-based instruction set accelerator. In: FCCM ’99: Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p. 92. IEEE Computer Society, Washington, DC (1999)

    Google Scholar 

  34. Lee, M.H., Singh, H., Lu, G., Bagherzadeh, N., Kurdahi, F.J., Filho, E.M.C., Alves, V.C.: Design and implementation of the morphosys reconfigurable computingprocessor. J. VLSI Signal Process. Syst. 24(2/3), 147–164 (2000). doi:http://dx.doi.org/10.1023/A:1008189221436

  35. Lee, W., Barua, R., Frank, M., Srikrishna, D., Babb, J., Sarkar, V., Amarasinghe, S.: Space-time scheduling of instruction-level parallelism on a raw machine. SIGOPS Oper. Syst. Rev. 32(5), 46–57 (1998). doi:http://doi.acm.org/10.1145/384265.291018

  36. Lee, W.A., Agarwal, L., Lee, T., Smith, A., Lam, E., Athanas, P., Ghosh, S.: PRISM-II compiler and architecture. Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, 9–16. IEEE Computer Society, Los Alamitos (1993). doi: http://doi.acm.org/10.1109/FPGA.1993.279484

  37. Lodi, A., Toma, M., Campi, F., Cappelli, A., Guerrieri, R.: A vliw processor with reconfigurable instruction set for embedded applications. IEEE J. Solid State Circuits 38(11), 1876–1886 (2003)

    Article  Google Scholar 

  38. Maheswaran, K., Akella, V.: Hazard-free implementation of the self-timed cell set in a xilinx fpga. Tech. rep., University of California (1994)

    Google Scholar 

  39. Mahlke, S.A., Lin, D.C., Chen, W.Y., Hank, R.E., Bringmann, R.A.: Effective compiler support for predicated execution using the hyperblock. In: MICRO 25: Proceedings of the 25th Annual International Symposium on Microarchitecture, pp. 45–54. IEEE Computer Society Press, Los Alamitos (1992). doi:http://doi.acm.org/10.1145/144953.144998

  40. Marshall, A., Stansfield, T., Kostarnov, I., Vuillemin, J., Hutchings, B.: A reconfigurable arithmetic array for multimedia applications. In: FPGA ’99: Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, pp. 135–143. ACM, New York (1999). doi:http://doi.acm.org/10.1145/296399.296444

  41. Mei, B., Vernalde, S., Verkest, D., De Man, H., Lauwerein, R.: ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In: Field-Programmable Logic and Applications. Lecture Notes in Computer Science, vol. 2778, pp. 61–70. Springer. Berlin/Heidelberg (2003). doi:10.1007/b12007. http://www.springerlink.com/content/03yt3xeh60r8971k/

  42. Mei, B., Vernalde, S., Verkest, D., De Man, H., Lauwereins, R., Mei, B., Vernalde, S., Verkest, D., De, H., Lauwerein, R.: DRESC: A retargetable compiler for coarse-grained reconfigurable architectures. Proceedings of 2002 IEEE International Conference on Field- Programmable Technology 166–173. IEEE Computer Society, Los Alamitos (2002). doi: http://doi.acm.org/10.1109/FPT.2002.1188678

  43. Mirsky, E., DeHon, A.: Matrix: A reconfigurable computing architecture with configurable instruction distribution and deployable resources. In: IEEE Symposium on FPGAs for Custom Computing Machines, pp. 157–166. IEEE Computer Society, Los Alamitos (1996)

    Google Scholar 

  44. Miyamori, T., Olukotun, K.: Remarc (abstract): reconfigurable multimedia array coprocessor. In: FPGA ’98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p. 261. ACM, New York (1998). doi:http://doi.acm.org/10.1145/275107.275164

  45. Miyamori, T., Olukotun, K.: Remarc: Reconfigurable multimedia array coprocessor. In: IEICE Trans. Info. Syst. E82-D:389–397 (1998)

    Google Scholar 

  46. Panainte, E.M., Bertels, K., Vassiliadis, S.: The molen compiler for reconfigurable processors. ACM Trans. Embed. Comput. Syst. 6(1), 6 (2007). doi:http://doi.acm.org/10.1145/1210268.1210274

    Google Scholar 

  47. Patel, S.J., Lumetta, S.S.: Replay: a hardware framework for dynamic optimization. IEEE Trans. Comput. 50(6), 590–608 (2001). doi:http://dx.doi.org/10.1109/12.931895

    Google Scholar 

  48. Rupp, C.R., Landguth, M., Garverick, T., Gomersall, E., Holt, H., Arnold, J.M., Gokhale, M.: The napa adaptive processing architecture. In: FCCM ’98: Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p. 28. IEEE Computer Society, Washington, DC (1998)

    Google Scholar 

  49. Salefski, B., Caglar, L.: Re-configurable computing in wireless. In: DAC ’01: Proceedings of the 38th annual Design Automation Conference, pp. 178–183. ACM, New York (2001). doi:http://doi.acm.org/10.1145/378239.378459

  50. Sankaralingam, K., Nagarajan, R., Liu, H., Kim, C., Huh, J., Ranganathan, N., Burger, D., Keckler, S.W., McDonald, R.G., Moore, C.R.: Trips: A polymorphous architecture for exploiting ilp, tlp, and dlp. ACM Trans. Archit. Code Optim. 1(1), 62–93 (2004). doi:http://doi.acm.org/10.1145/980152.980156

  51. Singh, H., hau Lee, M., Lu, G., Kurdahi, F.J., Bagherzadeh, N.: Morphosys: A reconfigurable architecture for multimedia applications. In: Workshop on Reconfigurable Computing at PACT, pp. 134–139 (1998)

    Google Scholar 

  52. Singh, H., Lee, M.H., Lu, G., Bagherzadeh, N., Kurdahi, F.J., Filho, E.M.C.: Morphosys: An integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Trans. Comput. 49(5), 465–481 (2000). doi:http://dx.doi.org/10.1109/12.859540

  53. Singh, H., Lee, M.H., Lu, G., Bagherzadeh, N., Kurdahi, F.J., Filho, E.M.C.: Morphosys: An integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Trans. Comput. 49(5), 465–481 (2000). doi:http://dx.doi.org/10.1109/12.859540

  54. Smith, M.J.S.: Application-Specific Integrated Circuits. Addison-Wesley Professional, Reading (2008)

    Google Scholar 

  55. Swanson, S., Michelson, K., Schwerin, A., Oskin, M.: Wavescalar. In: MICRO 36: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, p. 291. IEEE Computer Society, Washington, DC (2003)

    Google Scholar 

  56. Swanson, S., Schwerin, A., Mercaldi, M., Petersen, A., Putnam, A., Michelson, K., Oskin, M., Eggers, S.J.: The wavescalar architecture. ACM Trans. Comput. Syst. 25(2), 4 (2007). doi:http://doi.acm.org/10.1145/1233307.1233308

  57. Tatas, K., Siozios, K., Soudris, D.: A survey of existing fine-grain reconfigurable architectures and CAD tools. In: Fine- and Coarse-Grain Reconfigurable Computing, pp. 3–87. Springer, Dordrecht (2007). http://www.springerlink.com/content/m561311j78506281/

  58. Tau, E., Chen, D., Eslick, I., Brow, J.: A first generation dpga implementation. In: Proceedings of the Third Canadian Workshop on Field-Programmable Devices, pp. 138–143 (1995)

    Google Scholar 

  59. Taylor, M.B., Kim, J., Miller, J., Wentzlaff, D., Ghodrat, F., Greenwald, B., Hoffman, H., Johnson, P., Lee, J.W., Lee, W., Ma, A., Saraf, A., Seneski, M., Shnidman, N., Strumpen, V., Frank, M., Amarasinghe, S., Agarwal, A.: The raw microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE Micro. 22(2), 25–35 (2002). doi:http://dx.doi.org/10.1109/MM.2002.997877

    Google Scholar 

  60. Theodoridis, G., Soudris, D., Vassiliadis, S.: A survey of coarse-grain reconfigurable architectures and cad tools. In: Fine- and Coarse-Grain Reconfigurable Computing, pp. 89–149. Springer, Dordrecht (2007). http://www.springerlink.com/content/j118u3m6m225q264/

  61. Vassiliadis, N., Kavvadias, N., Theodoridis, G., Nikolaidis, S.: A risc architecture extended by an efficient tightly coupled reconfigurable unit. In: International Workshop On Applied Reconfigurable Computing (ARC), pp. 41–49. Springer, Berlin (2005)

    Google Scholar 

  62. Vassiliadis, S., Gaydadjiev, G., Bertels, K., Panainte, E.M.: The molen programming paradigm. In: Proceedings of the Third International Workshop on Systems, Architectures, Modeling, and Simulation, Lecture Notes in Computer Science, vol. 3133, pp. 1–10. Springer (2004)

    Google Scholar 

  63. Vassiliadis, S., Wong, S., Cotofana, S.: The molen rho-mu-coded processor. In: FPL ’01: Proceedings of the 11th International Conference on Field-Programmable Logic and Applications, pp. 275–285. Springer, London (2001)

    Google Scholar 

  64. Vassiliadis, S., Wong, S., Gaydadjiev, G., Bertels, K., Kuzmanov, G., Panainte, E.M.: The molen polymorphic processor. IEEE Trans. Comput. 53(11), 1363–1375 (2004). doi:http://dx.doi.org/10.1109/TC.2004.104

    Google Scholar 

  65. Waingold, E., Taylor, M., Srikrishna, D., Sarkar, V., Lee, W., Lee, V., Kim, J., Frank, M., Finch, P., Barua, R., Babb, J., Amarasinghe, S., Agarwal, A.: Baring it all to software: Raw machines. Computer 30(9), 86–93 (1997). doi:http://dx.doi.org/10.1109/2.612254

    Google Scholar 

  66. Wilson, R.P., French, R.S., Wilson, C.S., Amarasinghe, S.P., Anderson, J.M., Tjiang, S.W.K., Liao, S.W., Tseng, C.W., Hall, M.W., Lam, M.S., Hennessy, J.L.: Suif: an infrastructure for research on parallelizing and optimizing compilers. SIGPLAN Not. 29(12), 31–37 (1994). doi:http://doi.acm.org/10.1145/193209.193217

  67. Wirthlin, M.J.: A dynamic instruction set computer. In: FCCM ’95: Proceedings of the IEEE Symposium on FPGA’s for Custom Computing Machines, p. 99. IEEE Computer Society, Washington, DC (1995)

    Google Scholar 

  68. Wirthlin, M.J., Hutchings, B.L., Gilson, K.L.: The nano processor: A low resource reconfigurable processor. In: D.A. Buell, K.L. Pocek (eds.) IEEE Workshop on FPGAs for Custom Computing Machines, pp. 23–30. IEEE Computer Society, Los Alamitos (1994). citeseer.ist.psu.edu/wirthlin94nano.html

  69. Wittig, R.D., Chow, P.: Onechip: An fpga processor with reconfigurable logic. In: IEEE Symposium on FPGAs for Custom Computing Machines, pp. 126–135. IEEE Computer Society, Los Alamitos (1995)

    Google Scholar 

  70. Zhang, H., Prabhu, V., George, V., Wan, M., Benes, M., Abnous, A., Rabaey, J.: A 1-v heterogenous reconfigurable dsp ic for wireless baseband digital signal processing. IEEE J. Solid State Circuits 35(11), 1697–1704 (2000)

    Article  Google Scholar 

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  1. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Campus do Vale, Bloco IV, 15064, Porto Alegre, Brazil

    Antonio Carlos Schneider Beck

  2. Departamento de Informática e Matemática Aplicada, Universidade Federal do Rio Grande do Norte, Campus Universitário, Lagoa Nova, Natal, Brazil

    Monica Magalhães Pereira

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  1. Campus do Vale - Bloco IV, Departamento de Informática Aplicada, Instituto de Informática, Av. Bento Gonçalves, 9500, Porte Alegre - RS, 91501-970, Brazil

    Antonio Carlos Schneider Beck

  2. Instituto de Informática da UFRGS, Av. Bento Gonçalves, 9500 - Campus do Vale - Bloco IV, Bairro Agronomia, 91501-970, Brazil

    Carlos Arthur Lang Lisbôa

  3. , Dept de Informática Aplicada, Instituto de Informática da UFRGS, Av. Bento Gonçalves, 9500 - Campus do Vale - Bloco IV, Bairro Agronomia, 91501-970, Brazil

    Luigi Carro

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Beck, A.C.S., Pereira, M.M. (2013). Reconfigurable Systems. In: Beck, A., Lang Lisbôa, C., Carro, L. (eds) Adaptable Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1746-0_3

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