Abstract
This chapter presents a framework for the high-level optimization of time-interleaved ADCs. The results show that for interleaved flash ADCs, there is an optimal value for the interleaving factor, which is a function of the load capacitance of the dynamic comparators, the ADC resolution, the sampling rate, and the static power dissipation of the resistor ladder. An extension to transistor-level circuits is discussed, and the plotted results have a similar form to those of the high-level framework.
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© 2012 Springer Science+Business Media, LLC
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El-Chammas, M., Murmann, B. (2012). Architecture Optimization. In: Background Calibration of Time-Interleaved Data Converters. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1511-4_4
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DOI: https://doi.org/10.1007/978-1-4614-1511-4_4
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Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-1510-7
Online ISBN: 978-1-4614-1511-4
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