Introduction

Abstract

The increasing data rate of wireline communication systems leads to more inter-symbol interference, due to the dispersive properties of the communication channel. This requires more complex equalization blocks to meet the required bit-error rate. One solution is to use an Analog-to-Digital Converter (ADC) in the front-end, thus enabling a digitally-equalized serial link. To achieve the high-data rates of these communication systems, a time-interleaved ADC is typically used. However, this type of ADC suffers from several time-varying errors, the most prominent of which is timing skew. This book introduces a statistics-based background calibration algorithm that compensates for the effect of timing skew. To demonstrate the background calibration algorithm, a proof-of-concept 5 bit 12 GS/s flash ADC has been fabricated in a 65 nm CMOS process. The design of this ADC takes into consideration the tight power bounds imposed on serial links by optimizing both the time-interleaved and the sub-ADC architecture. Power consumption is further reduced by using calibration circuits to correct the offset of the flash ADC’s comparators. In the measured results, the timing skew correction improves the dynamic performance of the time-interleaved ADC by 12 dB, and the proof-of-concept ADC has the lowest published power consumption for ADCs with sample rates higher than 10 GS/s.