Skip to main content

Clocked Nanometer CMOS Comparators

  • Chapter
  • First Online:
Integrated Circuits for Analog Signal Processing
  • 3025 Accesses

Abstract

A circuit block, which is mostly used in the link between the analog and the digital domain, e.g. in an analog-digital converter (ADC), is the clocked, regenerative comparator. This type of comparator is implemented mostly in ADCs with a fast conversion rate, e.g. in flash-ADCs [1–4] because of its capability of a fast decision. A comparator is a circuit, which typically compares two analog input voltages (VA p , VA n ), currents or charges and delivers a logical level at the output, which indicates, what of the compared values was higher (see Fig. 8.1).

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 109.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 149.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Sandner C, Clara M, Santner A, Hartnig T, Kuttner F (2005) A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13μm Digital CMOS, IEEE proceedings of design, automation and test in Europe conference and exhibition (DATE’05), vol 3, pp 223–226

    Google Scholar 

  2. Uyttenhove K, Steyaert M (2001) A CMOS 6-bit, 1 GHz ADC for IF Sampling Applications, IEEE MTT-S international microwave symposium digest, vol 3, pp 2131–2134, May 2001

    Google Scholar 

  3. Park S, Palaskas Y, Flynn MP (2006) A 4GS/s 4b Flash ADC in 0.18μm CMOS, IEEE International Solid-State Circuits Conference, pp 570–571, Feb 2006

    Google Scholar 

  4. Paulus C, Blüthgen H-M, Löw M, Sicheneder E, Brüls N, Courtois A, Tiebout M, Thewes R (2004) A 4GS/s 6b Flash ADC in 0.13μm CMOS, Digest of symposium on VLSI circuits, pp 420–423, June 2004

    Google Scholar 

  5. Klar H (1996) Integrierte Digitale Schaltungen MOS/BICMOS. Springer, Berlin

    MATH  Google Scholar 

  6. Veendrick HJM (1980) The behaviour of flip-flops used as synchronizers and prediction of their failure rate. IEEE J Solid State Circ 15(2):169–176

    Article  Google Scholar 

  7. Gregorian R (1999) Introduction to CMOS Op-amps and comparators. Wiley, New York

    Google Scholar 

  8. Figueiredo PM, Vital JC (2006) Kickback noise reduction techniques for CMOS latched comparators. IEEE Trans Circ Syst II 53(7):541–545

    Article  Google Scholar 

  9. Lohstroh J (1983) Worst-case static noise margin criteria for logic circuits and their mathematical equivalence. IEEE J Solid State Circ 18(6):803–807

    Article  Google Scholar 

  10. Seevinck E, List FJ, Lohstroh J (1987) Static-noise margin analysis of MOS SRAM cells. IEEE J Solid State Circ 22(5):748–754

    Article  Google Scholar 

  11. Bhavnagarwala AJ, Tang X, Meindl JD (2001) The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J Solid State Circ 36(4):658–665

    Article  Google Scholar 

  12. Weinrichter H, Hlawatsch F (1991) Stochastische Grundlagen nachrichtentechnischer Signale. Springer, New York

    Book  Google Scholar 

  13. Nikoozadeh A, Murmann B (2006) An analysis of latch comparator offset due to load capacitor mismatch. IEEE Trans Circ Syst II 53(12):1398–1402

    Article  Google Scholar 

  14. Pelgrom MJM, Duinmaijer ACJ, Welbers APG (1989) Matching properties of MOS transistors. IEEE J Solid State Circ 24(5):1433–1440

    Article  Google Scholar 

  15. Lakshmikumar KR, Hadaway RA, Copeland MA (1986) Characterization and modeling of mismatch in MOS transistors for precision analog design. IEEE J Solid State Circ sc-21(6):1057–1066

    Google Scholar 

  16. Schneider K, Zimmermann H (2006) Highly sensitive optical receivers. Springer, Berlin

    Book  Google Scholar 

  17. Kobayashi T, Nogami K, Shirotori T, Fujimoto Y (1993) A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. IEEE J Solid State Circ 28(4):523–527

    Article  Google Scholar 

  18. Wicht B, Nirschl T, Schmitt-Landsiedel D (2004) Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J Solid State Circ 39(7):1148–1158

    Article  Google Scholar 

  19. Schinkel D, Mensink E, Klumpernik E, van Tuijl E, Nauta B (2007) A double-tail latch-type voltage sense amplifier with 18ps setup + hold time. IEEE international solid-state circuits conference, pp 314–315, Feb 2007

    Google Scholar 

  20. Annema A-J, Nauta B, van Langevelde R, Tuinhout H (2005) Analog circuits in ultra-deep-submicron CMOS. IEEE J Solid State Circ 40(1):132–143

    Article  Google Scholar 

  21. Goll B, Zimmermann H (2007) A 0.12μm CMOS comparator requiring 0.5V at 600MHz and 1.5V at 6GHz. IEEE international solid-state circuits conference, pp 316–317, Feb 2007

    Google Scholar 

  22. Goll B, Zimmermann H (2009) A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Trans Circ Syst II 56(11):810–814

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Bernhard Goll .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer Science+Business Media New York

About this chapter

Cite this chapter

Goll, B., Zimmermann, H. (2013). Clocked Nanometer CMOS Comparators. In: Tlelo-Cuautle, E. (eds) Integrated Circuits for Analog Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1383-7_8

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-1383-7_8

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-1382-0

  • Online ISBN: 978-1-4614-1383-7

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics