Skip to main content

Characterization and Specification

  • Chapter
  • First Online:
  • 5026 Accesses

Abstract

The specification of the converter is a dominant mechanism to align the wishes of the user to the possibilities of the designer. Directly coupled to the specification is the measurement technique that serves to establish a numerical value for a theoretical concept. This chapter discusses the fundamentals of the characterization and measurement techniques, such as histogram testing.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   89.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Seitzer D, Pretzl G, Hamdy NA (1983) Electronic analog-to-digital conversion. Wiley Interscience, New York. ISBN: 0-471-90198-9

    Google Scholar 

  2. van de Plassche R (1994) Integrated analog-to-digital and digital-to-analog converters. Kluwer Academic Publishers, the Netherlands. ISBN: 0-7923-9436-4 (2nd edition ISBN: 1-4020-7500-6, the Netherlands, 2003)

    Google Scholar 

  3. Razavi B (1994) Principles of data conversion system design. Wiley-IEEE Press, USA. ISBN: 978-0-7803-1093-3

    Google Scholar 

  4. Jespers P (2001) Integrated converters D-to-A and A-to-D architectures, analysis and simulation. Oxford Press, USA. ISBN: 0-19-856446-5

    Google Scholar 

  5. Maloberti F (2007) Data converters. Springer, Berlin. ISBN: 0-38-732485-2

    Google Scholar 

  6. Carmichael RD (1931) Smith ER Mathematical tables and formulas. Dover publications, New York. ISBN: 486-60111-0

    Google Scholar 

  7. Abramovic M, Stegun IA (eds) (1965) Handbook of mathematical functions. Dover publications, New York. ISBN: 0-486-61272-4

    Google Scholar 

  8. Beyer WH (1987) CRC standard mathematical tables, 28th edn. CRC press, Boca Raton. ISBN: 0-8493-0628-0

    Google Scholar 

  9. Sansen W (1999) Distortion in elementary transistor circuits. IEEE Trans Circ Syst II 46: 315–325

    Google Scholar 

  10. Rey WJJ (1983) Introduction to robust and quasi-robust statistical methods. Springer, Berlin. ISBN: 0-387-12866-2

    MATH  Google Scholar 

  11. Papoulis A (1965) Probability, random variables, and stochastic processes, student edn. McGrawHill, New York (4th edition ISBN: 0-073-66011-6, McGrawHill 2001)

    Google Scholar 

  12. Weast RC (ed) (1984) CRC handbook of chemstry and physics, 64th edn. CRC Press, Boca Raton. ISBN: 0-8493-0464-4

    Google Scholar 

  13. van der Pauw LJ (1958) A method of measuring specific resistivity and hall effect of discs of arbitrary shape. Philips Res Rep 13:1–9

    Google Scholar 

  14. Sze SM (1981) Physics of semiconductor devices, 2nd edn. Wiley, New York (3rd edition ISBN: 978-0-471-14323-9, 2006)

    Google Scholar 

  15. Black JR (1969) Electromigration: a brief survey and some recent results. IEEE Trans Electron Devices ED-16:338–347

    Google Scholar 

  16. Ogawa ET, Lee K-D, Blaschke VA, Ho PS (2002) Electromigration reliability issues in dual-damascene Cu interconnections. IEEE Trans Reliab 51:403–419

    Google Scholar 

  17. van der Ziel A (1986) Noise in solid-state devices and circuits. Wiley-lnterscience, New York. ISBN: 0-471-832340

    Google Scholar 

  18. Feynman RP, Leighton RB, Sands M (1977) The Feynman lectures on physics, 6th edn, vol 1,2, and 3. Addison Wesley Publishing Company, California. ISBN: 0-201-02010-6-H

    Google Scholar 

  19. Rosa EB (1908) The self and mutual inductances of linear conductors. Bull Bur of Stand 4:301–344

    Google Scholar 

  20. ITRS The national technology roadmap for semiconductors, technology needs. 1994–2011. Updates: http://www.itrs.net.

  21. Seto JYW (1975) The electrical properties of polycrystalline silicon films. J Appl Phys 46:5247–5254

    Google Scholar 

  22. de Graaff HC, Klaassen FM (1990) Compact transistor modeling for circuit design. Springer, Wien. ISBN: 3-211-82136-8

    Google Scholar 

  23. Ghandhi S (1957) Darlington’s compound connection for transistors. IRE Trans Circ Theor 4:291–292 (see also US patent 2-663-806)

    Google Scholar 

  24. McCreary JL (1981) Matching properties, and voltage and temperature dependence of MOS capacitors. IEEE J Solid-State Circ 16:608–616

    Google Scholar 

  25. Shyu J-B, Temes GC, Yao K (1982) Random errors in MOS capacitors. IEEE J Solid-State Circ 17:1070–1076

    Google Scholar 

  26. Aparicio R (2002) Capacity limits and matching properties of integrated capacitors. IEEE J Solid-State Circ 27:384–393

    Google Scholar 

  27. Bely M et al (2007) Capacitive integrated circuit structure. US patent 7-170-178

    Google Scholar 

  28. Wei C, Barrington RF, Mautz JR, Sarkar TK (1984) Multiconductor transmission lines in multilayered dielectric media. IEEE Trans Microw Theor Technol 32:439–450

    Google Scholar 

  29. Wallinga H, Bult K (1989) Design and analysis of CMOS analog signal processing circuits by means of a graphcal MOST model. IEEE J Solid-State Circ 24:672–680

    Google Scholar 

  30. Vertregt M (2006) The analog challenge of nanometer CMOS. In: Technical digest international electron devices meeting, IEDM Digest of Technical Papers, pp 1–8

    Google Scholar 

  31. Pelgrom MJM, Duinmaijer ACJ, Welbers APG (1989) Matching properties of MOS transistors. IEEE J Solid-State Circ 24:1433–1440

    Google Scholar 

  32. Woerlee PH, Knitel MJ, van Langevelde R, Klaassen DBM, Tiemeijer LF, Scholten AJ, Zegers-van Duijnhoven ATA (2001) RF-CMOS performance trends. IEEE Trans Electron Devices 48:1776–1782

    Google Scholar 

  33. Scholten AJ, Tiemeijer LF, De Vreede PWH, Klaassen DBM (1999) A large signal non-quasi-static MOS model for RF circuit simulation. In: Technical digest international electron devices meeting, pp 163–166

    Google Scholar 

  34. Meindl JD (1995) Low power microelectronics: retrospect and prospect. Proc of the IEEE 83:619–635

    Google Scholar 

  35. Klaassen FM, Hes W (1986) On the temperature coefficient of the MOSFET threshold voltage. Solid-State Electron 29:787–789

    Google Scholar 

  36. Scholten AJ, Tiemeijer LF, van Langevelde R, Havens RJ, Zegers-van Duijnhoven ATA, Venezia VC (2003) Noise modeling for RF CMOS circuit simulation. IEEE Trans Electron Devices 50:618–632

    Google Scholar 

  37. Brews JR (2006) MOSFET hand analysis using BSIM. IEEE Circ Devices Mag 21:28–36

    Google Scholar 

  38. Gildenblat G, Li X, Wu W, Wang H, Jha A, van Langevelde R, Smit GDJ, Scholten AJ, Klaassen DBM (2006) PSP: an advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans Electron Devices 53:1979–1993

    Google Scholar 

  39. Enz CC, Krummenacher F, Vittoz EA (1995) An analytical MOS transistor model valid in all regions of operations and dedicated to low- voltage and low-current applications. Analog Integr Circ Signal Process J 8:83–114

    Google Scholar 

  40. Sakurai T, Newton AR (1990) Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J Solid-State Circ 25:584–594

    Google Scholar 

  41. Lee MSL, Tenbroek BM, Redman-White W, Benson J, Uren MJ (2001) A physically based compact model of partially depleted MOSFETs for analog circuit stimulation. IEEE J Solid-State Circ 36:110–121

    Google Scholar 

  42. Middlebrook RD (2006) The general feedback theorem: a final solution for feedback systems. IEEE Microw Mag 7:50–63

    Google Scholar 

  43. Unbehauen R (1972) Synthese elektrischer Netzwerke. Oldenbourg Verlag, German

    Google Scholar 

  44. Sallen RP, Key EL (1955) A practical method of designing RC active filters. IRE Trans Circ Theor 2 CT-2:74–85

    Google Scholar 

  45. Nauta B (1992) Analog CMOS filters for very high frequencies. Kluwer Academic Publishers, Dordrecht. ISBN 0792392728

    Google Scholar 

  46. Berndt DF, Dutta Roy SC (1969) Inductor simulation with a single unity gain amplifier. IEEE J Solid State Circ 4:161–162

    Google Scholar 

  47. Martin K, Sedra A (1981) Effects of the op amp finite gain and bandwidth on the performance of switched-capacitor filters. IEEE Trans Circ Syst CAS-28:822–829

    Google Scholar 

  48. Huang Q, Sansen W (1987) Design techniques for improved capacitor area efficiency in switched-capacitor biquads. IEEE Trans Circ Syst CAS-34:1590–1599

    Google Scholar 

  49. Allen PE, Sanchez-Sinencio E (1984) Switched capacitor circuits. Van Nostrand Reinhold, New York. ISBN: 0-4422-0873-1

    Google Scholar 

  50. Allstot D, Black W (1983) Technological design consideration for monolithic MOS switched-capacitor filtering systems. Proc IEEE 71:967–986

    Google Scholar 

  51. Gregorian R, Temes GC (1986) Analog MOS integrated circuits for signal processing. Wiley, New York. ISBN: 0-471-09797-7

    Google Scholar 

  52. Johns D, Martin KW (1997) Analog integrated circuit design. Wiley, New York. ISBN: 0-471-14448-7

    Google Scholar 

  53. Schreier R, Silva J, Steensgaard J, Temes GC (2005) Design-oriented estimation of thermal noise in switched-capacitor circuits. IEEE Trans Circ Syst I 15:2358–2368

    Google Scholar 

  54. Gray PR, Meyer RG (1993) Analysis and design of analog integrated circuits, 3rd edn. Wiley, New York (4th edn, Wiley, New York, ISBN: 0-471-32168-0, 2001)

    Google Scholar 

  55. Allen P, Holberg D (1987) CMOS analog circuit design. Holt, Rinehart and Winston Inc, New York

    Google Scholar 

  56. Rijns JJF (1996) CMOS low-distortion high-frequency variable-gain amplifier. IEEE J Solid-State Circ 31:1029–1034

    Google Scholar 

  57. Krummenacher F, Joehl N (2009) A differential-ramp based 65 dB-linear VGA technique in 65 nm CMOS. IEEE J Solid-State Circ 44:2503–2514

    Google Scholar 

  58. Gilbert B (1968) A precise four-quadrant multiplier with subnanosecond response. IEEE J Solid-State Circ 3:365–373

    Google Scholar 

  59. Elwan H, Tekin A, Pedrotti K (1988) A 4-MHz CMOS continuous-time filter with on-chip automatic tuning. IEEE J. Solid-State Circ 23:750–758

    Google Scholar 

  60. Bult K, Geelen GJGM (1990) A fast-settling CMOS op amp for SC circuits with 90-dB DC gain. IEEE J Solid-State Circ 25:1379–1384

    Google Scholar 

  61. Sackinger E, Guggenbuhl W (1990) A high-swing, high-impedance MOS cascode circuit. IEEE J Solid-State Circ 25:289–298

    Google Scholar 

  62. Kamath BYT, Meyer RG, Gray PR (1974) Relationship between frequency response and settling time of operational amplifiers. IEEE J Solid-State Circ 9:347–352

    Google Scholar 

  63. Solomon J (1974) The monolitic op amp: a tutorial study. IEEE J Solid-State Circ 9:314–332

    Google Scholar 

  64. Tsividis Y, Gray P (1976) An integrated NMOS operational amplifier with internal compensation. IEEE J Solid-State Circ 11:748–754

    Google Scholar 

  65. Tsividis Y (1978) Design consideration in single-channel MOS analog lntegraied circuits–a tutorial. IEEE J Solid-State Circ 13:383–391

    Google Scholar 

  66. Gray PR, Meyer R (1982) MOS operational amplifier design a tutorial overview. IEEE J Solid-state Circ 17:969–982

    Google Scholar 

  67. Redman-White W (1997) A high bandwidth constant gm and slew-rate rail-to-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems. IEEE J Solid-State Circ 32:701–712

    Google Scholar 

  68. Ahuja B (1983) An improved frequency compensation technique for CMOS operational amplifiers. IEEE J Solid-state Circ 18:629–633

    MathSciNet  Google Scholar 

  69. Cherry EM, Hooper DE (1963) The design of wide-band transistor feedback amplifiers. Proc IEEE 110(2):375–389

    Google Scholar 

  70. Hermans C, Steyaert MSJ (2006) A high-speed 850-nm optical receiver front-end in 0.18μm CMOS. IEEE J Solid-State Circ 41:1606–1614

    Google Scholar 

  71. Leeson DB (1966) A simple model of feedback oscillator noise spectrum. Proc IEEE 54:329–330

    Google Scholar 

  72. Demir A (2006) Computing timing jitter from phase noise spectra for oscillators and phase-locked loops with white and 1 ∕ f noise. IEEE Trans Circ Syst I 53:1869–1884

    Google Scholar 

  73. Hajimiri A, Lee T (1998) A general theory of phase noise in electrical oscillators. IEEE J Solid-State Circ 33:179–194

    Google Scholar 

  74. Razavi B (1996) A study of phase noise in CMOS oscillators. IEEE J Solid-State Circ 31:331–343

    Google Scholar 

  75. van der Tang JD (2002) High frequency oscillator design for integrated transceivers. Ph.D. thesis, Technical University Eindhoven

    Google Scholar 

  76. Huang Q (2000) Phase noise to carrier ratio in LC oscillators. IEEE Trans Circ Syst I: Fundam Theor Appl 47:965–980

    Google Scholar 

  77. Vittoz E, Degrauwe M, Bitz S (1988) High-performance crystal oscillator circuits: theory and application. IEEE J Solid-state Circ 23:774–783

    Google Scholar 

  78. Thommen W (1999) An improved low-power crystal oscillator. In: 25th European solid-state circuits conference, pp 146–149

    Google Scholar 

  79. Santos JT, Meyer RG A one-pin crystal oscillator for VLSI circuits. IEEE J Solid-State Circ 19:228–236 (1984)

    Google Scholar 

  80. Geraedts P, van Tuijl E, Klumperink E, Wienk G, Nauta B (2008) A 90 μW 12 MHz relaxation oscillator with a -162dB FOM. In: International solid-state circuits conference, digest of technical papers, pp 348–349

    Google Scholar 

  81. Sebastiano F, Breems L, Makinwa K, Drago S, Leenaerts D, Nauta B (2009) A low-voltage mobility-based frequency reference for crystal-less ULP radios. IEEE J Solid-State Circ 44:2002–2009

    Google Scholar 

  82. Gao X, Klumperink EAM, Bohsali M, Nauta B (2009) A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N 2. IEEE J Solid-State Circ 44:3253–3263

    Google Scholar 

  83. Rabiner LR, Gold B (1975) Theory and application of digital signal processing. Prentice-Hall, Englewood Cliffs. ISBN: 0-139-141014

    Google Scholar 

  84. van den Enden AWM, Verhoeckx NAM (1989) Discrete time signal processing, an introduction. Prentice Hall, New Jersey. ISBN: 0-132-167557

    Google Scholar 

  85. Nyquist H (1928) Certain topics in telegraph transmission theory. Trans AIEE 47:617–644 (Reprinted in Proc IEEE 90:280–305, 2002)

    Google Scholar 

  86. Shannon CE (1948) A mathematical theory of communication. Bell Syst Technol J 27: 379–423 and 623–656

    Google Scholar 

  87. Shannon CE (1949) Communication in the presence of noise. Proc IRE 37:10–21 (Reprinted in Proc IEEE 86:447–457, 1998)

    Google Scholar 

  88. Unser M (2000) Sampling-50 years after Shannon. Proc IEEE 88:569–587

    Google Scholar 

  89. Candes E, Romberg J, Tao T (2006) Robust uncertainty principles: exact signal reconstruction from highly incomplete frequency information. IEEE Trans Inform Theor 52:489–509

    MathSciNet  MATH  Google Scholar 

  90. Shinagawa M, Akazawa Y, Wakimoto T (1990) Jitter analysis of high-speed sampling systems. IEEE J Solid-State Circ 25:220–224

    Google Scholar 

  91. McClellan JH, Parks TW, Rabiner LR (1973) A computer program for designing optimum FIR linear phase digital filters. IEEE Trans Audio Electroacoustics 21:506–526

    Google Scholar 

  92. Séquin CH, Tompsett MF (1975) Charge transfer devices, supplement 8 to advances in electronics and electron physics. Academic, New York

    Google Scholar 

  93. Crols J, Steyaert M (1994) Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages. IEEE J Solid-State Circ 29:936–942

    Google Scholar 

  94. Baschirotto A (1997) Castello R A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing. IEEE J Solid-State Circ 32:1979–1986

    Google Scholar 

  95. Keramat A, Tao Z (2000) A capacitor mismatch and gain insensitive 1.5-bit/stage pipelined A/D converter. In: Proceedings of the 43rd IEEE Midwest symposium on circuits and systems, pp 48–51

    Google Scholar 

  96. Dickson J (1976) On-chip high-voltage generation MNOS integrated circuits using an improved voltage multiplier technique. IEEE J Solid-State Circ 11:374–378

    Google Scholar 

  97. Knepper RW (1978) Dynamic depletion mode: An E/D mosfet circuit method for improved performance. IEEE J Solid-State Circ 13:542–548

    Google Scholar 

  98. Abo AM, Gray PR (1999) A 1.5-V, 10-bit, 14.3-MS/s CMOS pipe-line analog-to-digital converter. IEEE J Solid-State Circ 34:599–606

    MATH  Google Scholar 

  99. Limotyrakis S, Kulchycki SD, Su DK, Wooley BA (2005) A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC. IEEE J Solid-State Circ 40:1057–1067

    Google Scholar 

  100. Song BA, Tompsett MF, Lakshmikumar KR (1988) A 12-bit 1 -MS / s capacitor error-averaging pipelined A/D converter. IEEE J Solid-State Circ 23:1324–1333

    Google Scholar 

  101. Yang W, Kelly D, Mehr I, Sayuk MT, Singer L (2001) A 3-V 340-mW 14-b 75-MS/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE J Solid-State Circ 36:1931–1936

    Google Scholar 

  102. Gregoire BR, Moon U (2008) An Over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain. IEEE J Solid-State Circ 43:2620–2630

    Google Scholar 

  103. Wakimoto T, Akazawa Y (1993) Circuits to reduce distortion in the diode-bridge track-and-hold. IEEE J Solid-State Circ 28:384–387

    Google Scholar 

  104. Vorenkamp P, Verdaasdonk JPM (1992) Fully bipolar, 120-MS/s 10-b track-and-hold circuit. IEEE J Solid-State Circ 27:988–992

    Google Scholar 

  105. Harley Reeves A (1942) Electric signaling system. US Patent 2-272-070, 3 Feb 1942. Also French Patent 852-183 issued 1938, and British Patent 538-860 issued 1939

    Google Scholar 

  106. IEEE Std 1057-1994 (1994) IEEE standard for digitizing waveform recorders

    Google Scholar 

  107. IEEE 1241–2000 Standard for terminology and test methods for analog-to-digital converters. IEEE Std1241, 2000, ISBN: 0-7381-2724-8, revision 2007

    Google Scholar 

  108. Tilden SJ, Linnenbrink TE, Green PJ (1999) Overview of IEEE-STD-1241 standard for terminology and test methods for analog-to-digital converters. In: Instrumentation and measurement technology conference, pp 1498–1503

    Google Scholar 

  109. Bennett WR (1948) Spectra of quantized signals. Bell Syst Technol J 27:446–472

    Google Scholar 

  110. Blachman N (1985) The intermodulation and distortion due to quantization of sinusoids. IEEE Trans Acoustics Speech Signal Process ASSP 33:1417–1426

    Google Scholar 

  111. Oude Alink MS, Kokkeler ABJ, Klumperink EAM, Rovers KC, Smit G, Nauta B (2009) Spurious-free dynamic range of a uniform quantizer. IEEE Trans Circ Syst II: Express Briefs 56:434–438

    Google Scholar 

  112. Lloyd S (1982) Least squares quantization in PCM. IEEE Trans Inform Theor 28:129–137 (transcript from 1957 paper)

    Google Scholar 

  113. Max J (1960) Quantizing for minimum distortion. IRE Trans Inform Theor 6:7–12

    MathSciNet  Google Scholar 

  114. Wannamaker RA, Lipshitz SP, Vanderkooy J, Wright JN (2000) A theory of nonsubtractive dither. IEEE Trans on Signal Process 48:499–516

    Google Scholar 

  115. Hilbiber D (1964) A new semiconductor voltage standard. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp 32–33

    Google Scholar 

  116. Widlar RJ (1971) New developments in IC voltage regulators. IEEE J Solid-State Circ 6:2–7

    Google Scholar 

  117. Kuijk KE (1973) A precision reference voltage source. IEEE J Solid-State Circ 8:222–226

    Google Scholar 

  118. Brokaw AP (1974) A simple three-terminal IC bandgap reference. IEEE J Solid-State Circ 9:388–393

    Google Scholar 

  119. Pertijs MAP, Huijsing JH (2006) Precision temperature sensors in CMOS technology. Springer, New York, ISBN: 140205257X

    Google Scholar 

  120. Song BS, Gray PR (1983) A precision curvature-compensated CMOS bandgap reference. IEEE J Solid-State Circ 18:634–643

    Google Scholar 

  121. Banba H, Shiga H, Umezawa A, Miyaba T, Tanzawa T, Atsumi S, Sakui K (1999) A CMOS Band-gap reference circuit with sub 1-V operation. IEEE J Solid-State Circ 34:670–674

    Google Scholar 

  122. Petrescu V, Pelgrom MJM, Veendrick HJM, Pavithran P, Wieling J (2006) Monitors for a signal integrity measurement system. In: 32nd European solid-state circuits conference, pp 122–125

    Google Scholar 

  123. Petrescu V, Pelgrom MJM, Veendrick HJM, Pavithran P, Wieling J (2006) A signal-integrity self-test concept for debugging nanometer CMOS ICs. In: IEEE international solid-state circuits conference, digest of technical papers, pp 544–545 (2006)

    Google Scholar 

  124. Fayomi CJB, Wirth GI, Achigui HF, Matsuzawa A (2010) Sub 1 V CMOS bandgap reference design techniques: a survey. Analog Integr Circ Signal Process 62:141–157

    Google Scholar 

  125. Annema A-J (1999) Low-power bandgap references featuring DTMOSTs. IEEE J Solid-State Circ 34:949–955

    Google Scholar 

  126. Sansen WM, Op’t Eynde F, Steyaert M (1988) A CMOS temperature compensated current reference. IEEE J Solid-State Circ 23:821–823

    Google Scholar 

  127. Blauschild RA, Tucci PA, Muller RS, Meyer RG (1978) A new NMOS temperature-stable voltage reference. IEEE J Solid-State Circ 13:767–774

    Google Scholar 

  128. Song H-J, Kim C-K (1993) A temperature-stabilized SOI voltage reference based on threshold voltage difference between enhancement and depletion NMOSFET’s. IEEE J Solid-State Circ 28:671–677

    Google Scholar 

  129. van de Plassche RJ (1976) Dynamic element matching for high-accuracy monolithic D/A converters. IEEE J Solid-State Circ 21:795–800

    Google Scholar 

  130. Schoeff JA (1979) An inherently monotonic 12 bit DAC. IEEE J Solid-State Circ 24:904–911

    Google Scholar 

  131. Naylor JR (1983) A complete high-speed voltage output 16-bit monolithic DAC. IEEE J Solid-State Circ 28:729–735

    Google Scholar 

  132. Schouwenaars HJ, Dijkmans EC, Kup BMJ, van Tuijl EJM (1986) A monolithic dual 16-bit D/A converter. IEEE J Solid-State Circ 21:424–429

    Google Scholar 

  133. Groeneveld DWJ, Schouwenaars HJ, Termeer HAH, Bastiaansen CAA (1989) A self-calibration technique for monolithic high-resolution D/A converters. IEEE J Solid-State Circ 24:1517–1522

    Google Scholar 

  134. Schouwenaars HJ, Groeneveld DWJ, Termeer HAH (1988) A low-power stereo 16-bit CMOS D/A converter for digital audio. IEEE J Solid-State Circ 23:1290–1297

    Google Scholar 

  135. Lin C-H, Bult K (1998) A 10-b 250-M sample/s CMOS DAC in 1 mm2. In: IEEE International solid-state circuits conference, digest of technical papers, pp 214–215

    Google Scholar 

  136. Van Den Bosch A, Borremans M, Steyaert M, Sansen W (2001) A 12 b 500 MS/s current-steering CMOS D/A converter. In: IEEE international solid-state circuits conference, digest of technical papers, pp 366–367

    Google Scholar 

  137. Van Den Bosch A, Borremans M, Steyaert M, Sansen W (2001) A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter. IEEE J Solid-State Circ 36:315–324

    Google Scholar 

  138. Bastiaansen CAA, Groeneveld DWJ, Schouwenaars HJ, Termeer HAH (1991) A 10-b 40-MHz 0.8-μm CMOS current-output D/A converter. IEEE J Solid-State Circ 26:917–921

    Google Scholar 

  139. Doris K, Briaire J, Leenaerts D, Vertregt M, van Roermund A (2005) A 12b 500MS/s DAC with > 70 dB SFDR up to 120MHz in 0.18μm CMOS. In: IEEE international solid-state circuits conference, digest of technical papers, pp 116–588

    Google Scholar 

  140. Van der Plas GAM, Vandenbussche J, Sansen W, Steyaert MSJ, Gielen GGE (1999) A 14-bit intrinsic accuracy Q 2 random walk CMOS DAC. IEEE J Solid-State Circ 34:1708–1718

    Google Scholar 

  141. Jewett B, Liu J, Poulton K (2005) A 1.2GS/s 15b DAC for precision signal generation. In: IEEE international solid-state circuits conference, digest of technical papers, pp 110–111

    Google Scholar 

  142. Park S, Kim G, Park S-C, Kim W (2002) A digital-to-analog converter based on differential-quad switching. IEEE J Solid-State Circ 37:1335–1338

    Google Scholar 

  143. Engel G, Kuo S, Rose S (2012) A 14b 3/6GHz current-steering RF DAC in 0.18m CMOS with 66dB ACLR at 2.9GHz. In: International solid-state circuits conference, digest of technical papers, pp 458–449

    Google Scholar 

  144. Schafferer B, Adams R (2004) A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications. In: IEEE international solid-state circuits conference, digest of technical papers, pp 360–361

    Google Scholar 

  145. Schofield W, Mercer D, Onge LS (2003) A 16b 400MS/s DAC with <  − 80dBc IMD to 300MHz and <  − 160dBm/Hz noise power spectral density. In: IEEE international solid-state circuits conference, digest of technical papers, pp 126–127

    Google Scholar 

  146. Su DK, Wooley BA (1993) A CMOS oversampling D/A converter with a current-mode semidigital reconstruction filter. IEEE J Solid-State Circ 28:1224–1233

    Google Scholar 

  147. Barkin DB, Lin ACY, Su DK, Wooley BA (2004) A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering. IEEE J Solid-State Circ 39:585–593

    Google Scholar 

  148. Suarez RE, Gray PR, Hodges DA (1975) All-MOS charge-redistribution analog-to-digital conversion techniques, II. IEEE J Solid-State Circ 10:379–385

    Google Scholar 

  149. Song B-S, Lee S-H, Tompsett MF (1990) A 10-b 15-MHz CMOS recycling two-step A/D converter. IEEE J Solid-State Circ 25:1328–1338

    Google Scholar 

  150. Philips K, van den Homberg J, Dijkmans C (1999) PowerDAC: a single-chip audio DAC with a 70%-efficient power stage in 0.5 μm CMOS. In: IEEE international solid-state circuits conference, digest of technical papers, pp 154–155

    Google Scholar 

  151. Fan Q, Huijsing JH, Makinwa KAA (2012) A 21 nV √ {Hz} Hz chopper-stabilized multi-path current-feedback instrumentation amplifier with 2 μV offset. IEEE J Solid-State Circ 47: 464-475

    Google Scholar 

  152. Blanken PG, Menten SEJ (2002) A 10 μV-offset 8 kHz bandwidth 4th-order chopped ΣΔ A/D converter for battery management. In: IEEE international solid-state circuits conference, digest of technical papers, pp 388–389

    Google Scholar 

  153. Carley L (1989) A noise-shaping coder topology for 15+ bit converters. IEEE J Solid-State Circ 24:267–273

    Google Scholar 

  154. Nys OJAP, Henderson RK (1996) An analysis of dynamic element matching techniques in sigma-delta modulation. In: IEEE international symposium on circuits and systems, pp 231–234

    Google Scholar 

  155. Henderson RK, Nys OJAP (1996) Dynamic element matching techniques with arbitrary noise shaping function. In: IEEE international symposium on circuits and systems, pp. 293–296

    Google Scholar 

  156. Story MJ (1992) Digital to analog converter adapted to select input sources based on a preselected algorithm once per cycle of a sampling signal. US patent 5-138-317

    Google Scholar 

  157. Maloberti A (1991) Convertitore digitale analogico sigma-delta multilivello con matching dinamico degli elementi. Tesi di Laurea, Universita degli Studi di Pavia, 1990–1991 (this thesis was not available)

    Google Scholar 

  158. Miller MR, Petrie CS (2003) A multibit sigma-delta ADC for multimode receivers. IEEE J Solid-State Circ 38:475–482

    Google Scholar 

  159. Risbo L, Hezar R, Kelleci B, Kiper H, Fares M (2011) A 108dB-DR 120dB-THD and 0.5Vrms output audio DAC with inter-symbol-interference-shaping algorithm in 45nm CMOS. In: IEEE international solid-state circuits conference, digest of technical papers, pp 484–485

    Google Scholar 

  160. Dingwall AGF, Zazzu V (1985) An 8-MHz CMOS subranging 8-bit A/D converter. IEEE J Solid-State Circ 20:1138–1143

    Google Scholar 

  161. Abrial A, Bouvier J, Fournier J, Senn P, Viellard M (1988) A 27-MHz digital-to-analog video processor. IEEE J Solid-State Circ 23:1358–1369

    Google Scholar 

  162. Pelgrom MJM (1990) A 10b 50MHz CMOS D/A converter with 75Ω buffer. IEEE J Solid-State Circ 25:1347–1352

    Google Scholar 

  163. Miki T, Nakamura Y, Nakaya M, Asai S, Akasaka Y, Horiba Y (1986) An 80-MHz 8-bit CMOS D/A converter. IEEE J Solid-State Circ 21:983–988

    Google Scholar 

  164. Pelgrom MJM, Roorda M (1988) An algorithmic 15 bit CMOS digital-to-analog converter. IEEE J Solid-State Circ 23:1402–1405

    Google Scholar 

  165. Matsumoto H, Watanabe K (1986) Switched-capacitor algorithmic digital-to-analog converters. IEEE Trans Circ Syst 33:721–724

    Google Scholar 

  166. Fiedler HL, Hoefflinger B, Demmer W, Draheim P (1981) A 5-bit building block for 20 MHz A/D converters. IEEE J Solid-State Circ 26:151–155

    Google Scholar 

  167. Wu J-T, Wooley BA (1988) A 100-MHz pipelined CMOS comparator. IEEE J Solid-State Circ 23:1379–1385

    Google Scholar 

  168. Nauta B, Venes AGW (1995) A 70 Ms/s 110 mW 8-b CMOS folding and interpolating A/D converter. IEEE J Solid-State Circ 30:1302–1308

    Google Scholar 

  169. Yin G, Op’t Eynde F, Sansen W (1992) A high-speed CMOS comparator with 8-b resolution. IEEE J Solid-State Circ 37:208–211

    Google Scholar 

  170. Venes AGW, van de Plassche RJ (1996) An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing. IEEE J Solid-State Circ 31: 1846–1853

    Google Scholar 

  171. Ellersick W, Chih-Kong KY, Horowitz M, Dally W (1999) GAD: a 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link. In: Symposium on VLSI circuits, digest of technical papers, pp 49–52

    Google Scholar 

  172. Montanaro J et al (1996) A 160 MHz, 32b, 0.5W CMOS RISC microprocessor. IEEE J Solid-State Circ 31:1703–1714

    Google Scholar 

  173. Verbruggen B, Craninckx J, Kuijk M, Wambacq P, Van der Plas G (2008) A 2.2mW 5b 1.75GS/s folding flash ADC in 90nm digital CMOS. In: IEEE international solid-state circuits conference, digest of technical papers, pp 252–611

    Google Scholar 

  174. Schinkel D, Mensink E, Klumperink E, van Tuijl E, Nauta B (2007) A double-tail latch-type voltage sense amplifier with 18ps setup+hold time. In: IEEE international solid-state circuits conference, digest of technical papers, pp 314–315

    Google Scholar 

  175. Fukushima N, Yamada T, Kumazawa N, Hasegawa Y, Soneda M (1989) A CMOS 40MHz 8b 105mW two-step ADC. In: International solid-state circuits conference, digest of technical papers, pp 14–15

    Google Scholar 

  176. Atherton JH, Simmonds HT (1992) An offset reduction technique for use with CMOS integrated comparators and amplifiers. IEEE J Solid-State Circ 27:1168–1175

    Google Scholar 

  177. Wong K-LJ, Yang C-KK (2004) Offset compensation in comparators with minimum input-referred supply noise. IEEE J Solid-State Circ 37:837–840

    Google Scholar 

  178. Kusumoto K, Matsuzawa A, Murata K (1993) A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC. IEEE J Solid-State Circ 28:1200–1206

    Google Scholar 

  179. Haas M, Draxelmayr D, Kuttner F, Zojer B (1990) A monolithic triple 8-bit CMOS video coder. IEEE Trans Consum Electron 36:722–729

    Google Scholar 

  180. Schvan P, Pollex D, Wang S-C, Falt C, Ben-Hamida N (2006) A 22GS/s 5b ADC in 0.13m SiGe BiCMOS. In: International solid-state circuits conference, digest of technical papers, pp 572–573

    Google Scholar 

  181. Reyhani H, Quinlan P (1994) A 5 V, 6-b, 80 Ms/s BiCMOS flash ADC. IEEE J Solid-State Circ 29:873–878

    Google Scholar 

  182. Vorenkamp P, Verdaasdonk JPM (1992) A 10b 50MHz pipelined ADC. In: International solid-state circuits conference, digest of technical papers, pp 32–33

    Google Scholar 

  183. Kattmann K, Barrow J (1991) A technique for reducing differential nonlinearity errors in flash A/D converters. In: International solid-state circuits conference, digest of technical papers, pp 170–171

    Google Scholar 

  184. Scholtens PCS, Vertregt M (2002) A 6-b 1.6-Gsample/s flash ADC in 0.18μm CMOS using averaging termination. IEEE J Solid-State Circ 37:1599–1609

    Google Scholar 

  185. Bult K, Buchwald A (1997) An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2. IEEE J Solid-State Circ 32:1887–1895

    Google Scholar 

  186. Uyttenhove K, Vandenbussche J, Lauwers E, Gielen GGE, Steyaert MSJ (2003) Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter. IEEE J Solid-State Circ 38:483–494

    Google Scholar 

  187. Van De Grift REJ, Rutten IWJM, van der Veen M (1987) An 8-bit video ADC incorporating folding and interpolation techniques. IEEE J Solid-State Circ 22:944–953

    Google Scholar 

  188. Vorenkamp P, Roovers R (1997) A 12-b, 60-MS/s cascaded folding and interpolating ADC. IEEE J Solid-State Circ 32:1876–1886

    Google Scholar 

  189. Van De Plassche RJ, van der Grift REJ (1979) A high-speed 7 bit A/D converter. IEEE J Solid-State Circ 14:938–943

    Google Scholar 

  190. Hoogzaad G, Roovers R (1999) A 65-mW, 10-bit, 40-MS/s BiCMOS Nyquist ADC in 0.8 mm2. IEEE J Solid-State Circ 34:1796–1802

    Google Scholar 

  191. Choe MJ, Song B-S, Bacrania K (2000) A 13b 40MS/s CMOS pipelined folding ADC with background offset trimming. In: International solid-state circuits conference, digest of technical papers, pp 36–37

    Google Scholar 

  192. Lewis SH, Gray PR (1987) A pipelined 5-MS/s 9-bit analog-to-digital converter. IEEE J Solid-State Circ 22:954–961

    Google Scholar 

  193. van der Ploeg H, Vertregt M, Lammers M (2006) A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications. IEEE J Solid-State Circ 41:1572–1577

    Google Scholar 

  194. Shimizu Y, Murayama S, Kudoh K, Yatsuda H, Ogawa A (2006) A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOS. In: International solid-state circuits conference, digest of technical papers, pp 802–803

    Google Scholar 

  195. Moreland C, Murden F, Elliott M, Young J, Hensley M, Stop R (2000) A 14b 100MS/s subranging ADC. IEEE J Solid-State Circ 35:1791–1798

    Google Scholar 

  196. McCharles R, Hodges D (1978) Charge circuits for analog LSI. IEEE Trans Circ Syst 25:490–497

    Google Scholar 

  197. Cho TB, Gray PR (1995) A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. IEEE J Solid-State Circ 30:166–172

    Google Scholar 

  198. Chai Y, Wu J-T (2012) A 5.37mW 10b 200MS/s dual-path pipelined ADC. In: International solid-state circuits conference, digest of technical papers, pp 462–463

    Google Scholar 

  199. Li PW, Chin MJ, Gray PR, Castello R (1984) A ratio-independent algorithmic analog-to-digital conversion technique. IEEE J Solid-State Circ 19:828–836

    Google Scholar 

  200. Karanicolas AN, Lee H-S, Barcrania KL (1993) A 15-b 1-MS/s digitally self-calibrated pipeline ADC. IEEE J Solid-State Circ 28:1207–1215

    Google Scholar 

  201. Nagaraj K, Fetterman HS, Anidjar J, Lewis SH, Renninger RG (1997) A 250-mW, 8-b, 52-MSs/s parallel-pipelined A/D converter with reduced number of amplifiers. IEEE J Solid-State Circ 32:312–320

    Google Scholar 

  202. Chiu Y, Gray PR, Nikolic B (2004) A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR. IEEE J Solid-State Circ 39:2139–2151

    Google Scholar 

  203. Wang X, Hurst PJ, Lewis SH (2004) A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration. IEEE J Solid-State Circ 39:1799–1808

    Google Scholar 

  204. Murmann B, Boser BE (2003) A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE J Solid-State Circ 38:2040–2050

    Google Scholar 

  205. Iroaga E, Murmann B (2007) A 12-Bit 75-MS/s pipelined ADC using incomplete settling. IEEE J Solid-State Circ 42:748–756

    Google Scholar 

  206. Geelen G, Paulus E, Simanjuntak D, Pastoor H, Verlinden R (2006) A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-step. In: International solid-state circuits conference, digest of technical papers, 214–215

    Google Scholar 

  207. Bardsley S, Dillon C, Kummaraguntla R, Lane C, Ali AMA, Rigsbee B, Combs D (2006) A 100-dB SFDR 80-MSPS 14-Bit 0.35-μm BiCMOS Pipeline ADC. IEEE J Solid-State Circ 41:2144–2153

    Google Scholar 

  208. Lee BG, Min BM, Manganaro G, Valvano JW (2008) A 14b 100 MS/s pipelined ADC with a merged active S/H and first MDAC. In: International solid-state circuits conference, digest of technical papers, pp 248–249

    Google Scholar 

  209. van de Vel H, Buter B, Ploeg Hvd, Vertregt M, Geelen G, Paulus E (2009) A 1.2 V 250-mW 14-b 100 MS/s digitally calibrated pipeline ADC in 90-nm CMOS. IEEE J Solid-State Circ 44:1047–1056

    Google Scholar 

  210. Lee CC, Flynn MP (2011) A SAR-assisted two-stage pipeline ADC. IEEE J Solid-State Circ 46:859–869

    Google Scholar 

  211. Verbruggen B, Iriguchi M, Craninckx J (2012) A 1.7mW 11b 250MS/s 2 interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS. In: International solid-state circuits conference, digest of technical papers, pp 466–467

    Google Scholar 

  212. Min BM, Kim P, Bowman FW, Boisvert DM, Aude AJ (2003) A 69-mW 10-bit 80-MS/s pipelined CMOS ADC. IEEE J Solid-State Circ 38:2031–2039

    Google Scholar 

  213. Mehr I, Singer L (2000) A 55-mW 10-bit 40-MS/s Nyquist-rate CMOS ADC. IEEE J Solid-State Circ 35:318–323

    Google Scholar 

  214. Sepke T, Fiorenza JK, Sodini CG, Holloway P, Lee H-S (2006) Comparator-based switched-capacitor circuits for scaled CMOS technologies. In: International solid-state circuits conference, digest of technical papers, pp 812–821

    Google Scholar 

  215. Brooks L, Lee H-S (2009) A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB. In: International solid-state circuits conference, digest of technical papers, pp 166–167

    Google Scholar 

  216. Wang H, Wang X, Hurst PJ, Lewis SH (2009) Nested digital background calibration of a 12-bit pipelined ADC without an input SHA. IEEE J Solid-State Circ 44:2780–2789

    Google Scholar 

  217. McCreary JL, Gray PR (1975) All-MOS charge redistribution analog-to-digital conversion techniques I. IEEE J Solid-State Circ 10:371–379

    Google Scholar 

  218. Craninckx J, Van der Plas G (2007) A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b cHARGE-sHaring SAR ADC in 90nm digital CMOS. In: International solid-state circuits conference, digest of technical papers, pp 246–247

    Google Scholar 

  219. Agnes A, Bonizzoni E, Malcovati P, Maloberti F (2008) A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with time-domain comparator. In: International solid-state circuits conference, digest of technical papers, pp 246–247

    Google Scholar 

  220. van Elzakker M, van Tuijl E, Geraedts P, Schinkel D, Klumperink E, Nauta B (2008) A 1.9μW 4.4fJ/conversion-step 10b 1MS/s charge-redistribution ADC. In: International solid-state circuits conference, digest of technical papers, pp 244–245

    Google Scholar 

  221. Harpe P, Zhang Y, Dolmans G, Philips K, de Groot H (2012) A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step. In: International solid-state circuits conference, digest of technical papers, pp 472–473

    Google Scholar 

  222. Kuttner F (2002) A 1.2V 10 b 20 MS/s non-binary successive approximation ADC in 0.13μm CMOS. In: International solid-state circuits conference, digest of technical papers, pp 176–177

    Google Scholar 

  223. Hesener M, Ficher T, Hanneberg A, Herbison D, Kuttner F, Wenskel H (2007) A 14b 4OMS/s redundant SAR ADC with 480MHz in 0.13pm CMOS. In: International solid-state circuits conference, digest of technical papers, pp 248–249

    Google Scholar 

  224. Shih C, Gray PR (1986) Reference refreshing cyclic analog-to-digital and digital-to-analog converters. IEEE J Solid-State Circ 21:544–554

    Google Scholar 

  225. Ginetti B, Jespers P, Vandemeulebroecke A (1992) A CMOS 13-b cyclic. A/D converter. IEEE J Solid-State Circ 27:957–964

    Google Scholar 

  226. Mase M, Kawahito S, Sasaki M, Wakamori Y, Furuta M (2005) A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters. IEEE J Solid-State Circ 40:2787–2795

    Google Scholar 

  227. Snoeij MF, Theuwissen AJP, Makinwa KAA, Huijsing JH (2007) Multiple-ramp column-parallel ADC architectures for CMOS image sensors. IEEE J Solid-State Circ 42:2986–2977

    Google Scholar 

  228. Naraghi S, Courcy M, Flynn MP (2009) A 9b 14 μW 0.06mm2 PPM ADC in 90nm digital CMOS. In: IEEE international solid-state circuits conference digest of technical papers, pp 168–169

    Google Scholar 

  229. Howard BK (1955) Binary quantizer. US patent 2-715-678

    Google Scholar 

  230. van der Ploeg H, Hoogzaad G, Termeer HAH, Vertregt M, Roovers RLJ (2001) A 2.5V, 12b, 54MS/s, 0.25um CMOS ADC. In: International solid-state circuits conference, digest of technical papers, pp 132–133

    Google Scholar 

  231. Pelgrom MJM, Jochijms A, Heijns H (1987) A CCD delay line for video applications. IEEE Trans Consum Electron 33:603–609

    Google Scholar 

  232. Kurosawa N, Kobayashi H, Maruyama K, Sugawara H, Kobayashi K (2001) Explicit analysis of channel mismatch effects in time-interleaved ADC systems. IEEE Trans Circ Syst I: Fundam Theor Appl 48:261–271

    Google Scholar 

  233. Doris K, Janssen E, Nani C, Zanikopoulos A, Wiede Gvd (2011) A 480 mW 2.6 GS/s 10b time-interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS. IEEE J Solid-State Circ 46:2821–2833

    Google Scholar 

  234. Hsu C-C, Huang F-C, Shih C-Y, Huang C-C, Lin Y-H, Lee C-C, Razavi B (2007) An 11b 800MS/s time-interleaved ADC with digital background calibration. In: International solid-state circuits conference, digest of technical papers, pp 164–165

    Google Scholar 

  235. Vertregt M, Dijkstra MB, Rens ACv, Pelgrom MJM (1993) A Versatile digital CMOS video delay line with embedded ADC, DAC and RAM. In: 19th European solid-state circuits conference, pp 226–229

    Google Scholar 

  236. Pelgrom MJM, Rens ACv, Vertregt M, Dijkstra MB (1994) A 25-Ms/s 8-bit CMOS A/D converter for embedded application. IEEE J Solid-State Circ 29:879–886

    Google Scholar 

  237. Murray B, Menting H (1992) A highly integrated D2MAC decoder. In: IEEE international conference on consumer electronics, digest of technical papers, pp 56–57

    Google Scholar 

  238. Mark JW, Todd TD (1981) A nonuniform sampling approach to data compression. IEEE Trans Commun 29:24–32

    Google Scholar 

  239. Allier E, Goulier J, Sicard G, Dezzani A, Andre E, Renaudin M (2005) A 120nm low power asynchronous ADC. In: International symposium on low-power electronics and design, pp 60–65

    Google Scholar 

  240. Trakimas M, Sonkusale SR (2011) An adaptive resolution asynchronous adc architecture for data compression in energy constrained sensing applications. IEEE Trans Circ Syst I 58: 921–934

    MathSciNet  Google Scholar 

  241. Lin C-S, Liu B-D (2003) A new successive approximation architecture for low-power low-cost CMOS A/D converter. IEEE J Solid-State Circ 38:54–62

    Google Scholar 

  242. Chen S-WM, Brodersen RW (2006) A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS. IEEE J Solid-State Circ 41:2669–2680

    Google Scholar 

  243. Pernillo J, Flynn MP (2011) A 1.5-GS/s flash ADC With 57.7-dB SFDR and 6.4-bit ENOB in 90 nm digital CMOS. IEEE Trans Circ Syst II: Express Briefs 58:837–841

    Google Scholar 

  244. Jansson J-P, Mantyniemi A, Kostamovaara J (2006) A CMOS time-to-digital converter with better than 10 ps single-shot precision. IEEE J Solid-State Circ 41:1286–1296

    Google Scholar 

  245. Chen P, Liu S-L, Wu J (2000) A CMOS pulse-shrinking delay element for time interval measurement. IEEE Trans Circ Syst 47:954–958

    Google Scholar 

  246. Rahkonen TE, Kostamovaara JT (1993) The use of stabilized CMOS delay lines for the digitization of short time intervals. IEEE J Solid-State Circ 28:887–894

    Google Scholar 

  247. van der Ploeg H (1997) The Nonius analog-to-digital converter. In: Internal Philips research report/ University Twente B.Sc. report, supervisor M. Pelgrom

    Google Scholar 

  248. Groza VZ (2001) High-resolution floating-point ADC. IEEE Trans Instrumentation and Measurement 50:1812–1829

    Google Scholar 

  249. de Jager F (1952) Delta modulation, a method of PCM transmission using the 1-unit code. Philips Res Rep 7:442–466

    Google Scholar 

  250. Cutler C (1960) Transmission systems employing quantization. US Patent 2-927-962

    Google Scholar 

  251. Widrow B (1956) A study of rough amplitude quantization by means of Nyquist sampling theory. IRE Trans Circ Theor CT-3:266–276

    Google Scholar 

  252. Inose H, Yasuda Y, Murakami J (1962) A telemetering system by code modulation- ΔΣ modulation. IRE Trans Space Electron Telemetry SET-8:204–209 (Proc IEEE 51:1524–1535, 1963)

    Google Scholar 

  253. Candy JC, Temes GC (eds) (1992) Oversampling delta-sigma data converters: theory, design and simulation. IEEE, New York

    Google Scholar 

  254. Norsworthy SR, Schreier R, Temes GC (eds) (1997) Delta-sigma data converters: theory, design, and simulation. IEEE Press, Piscataway. ISBN: 0-7803-1045-4

    Google Scholar 

  255. Schreier R, Temes GC (2004) Understanding delta-sigma data converters. Wiley, New York. ISBN: 0-471-46585-2

    Google Scholar 

  256. Naus PJA, Dijkmans EC (1991) Multi-bit oversampled ΣΔ A/D converters as front-end for CD players. IEEE J Solid-State Circ 26:905–909

    Google Scholar 

  257. Kup BMJ, Dijkmans EC, Naus PJA, Sneep J (1991) A bit-stream digital-to-analog converter with 18-b resolution. IEEE J Solid-State Circ 26:1757–1763

    Google Scholar 

  258. Naus PJA, Dijkmans EC, Stikvoort EF, Holland DJ, Bradinal W (1987) A CMOS stereo 16-bit D/A converter for digital audio. IEEE J Solid-State Circ 22:390–395

    Google Scholar 

  259. Adams R, Nguyen KQ (1998) A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling. IEEE J Solid-State Circ 33:1871–1878

    Google Scholar 

  260. Naus PJA, Dijkmans EC (1988) Low signal level distortion in sigma-delta modulators. In: 84th convention of the audio engineering society, Paris

    Google Scholar 

  261. Vleugels K, Rabii S, Wooley BA (2001) A 2.5 v sigma-delta modulator for broadband communications applications. IEEE J Solid-State Circ 36:1887–1889

    Google Scholar 

  262. Hart A, Voinigescu SP (2009) A 1 GHz bandwidth low-pass sigma-delta ADC with 20-50 GHz adjustable sampling rate. IEEE J Solid-State Circ 44:1401–1414

    Google Scholar 

  263. Gambini S, Rabaey J (2007) A 100-kS/s 65-dB DR sigma-delta ADC with 0.65V supply voltage. In: 33th European solid state circuits conference, pp 202–205

    Google Scholar 

  264. Lee WL, Sodini CG (1987) A topology for higher order interpolative coders. In: Proceedings of the IEEE international symposium on circuits and systems, pp 459–462

    Google Scholar 

  265. Chao KC-H, Nadeem S, Lee WL, Sodini CG (1990) A higher order topology for interpolative modulators for oversampling A/D converters. IEEE Trans Circ Syst 37:309–318

    Google Scholar 

  266. Williams III LA, Wooley BA (1994) A third-order sigma-delta modulator with extended dynamic range. IEEE J Solid-State Circ 29:193–202

    Google Scholar 

  267. Christen T, Burger T, Huang Q (2007) A 0.13μm CMOS EDGE/UMTS/WLAN tri-mode ADC with -92dB THD. In: International solid-state circuits conference, digest of technical papers, pp 240–241

    Google Scholar 

  268. Breems LJ, Rutten R, van Veldhoven RHM, van der Weide G (2007) A 56 mW continuous-time quadrature cascaded ΣΔ modulator with 77 dB DR in a near zero-IF 20 MHz Band. IEEE J Solid-State Circ 42:2696–2705

    Google Scholar 

  269. Kulchycki SD, Trofin R, Vleugels K, Wooley BA (2008) A 77-dB dynamic range, 7.5-MHz hybrid continuous-time/discrete-time cascaded sigma delta modulator. IEEE J Solid-State Circ 43:796–804

    Google Scholar 

  270. Breems LJ, Dijkmans EC, Huijsing JH (2001) A quadrature data-dependent DEM algorithm to improve image rejection of a complex ΣΔ modulator. IEEE J Solid-State Circ 36:1879–1886

    Google Scholar 

  271. van der Zwan EJ, Dijkmans EC (1996) A 0.2 mW CMOS ΣΔ modulator for speech coding with 80 dB dynamic range. IEEE J Solid-State Circ 31:1873–1880

    Google Scholar 

  272. Keller M, Buhmann A, Sauerbrey J, Ortmanns M, Manoli Y (2008) A comparative study on excess-loop-delay compensation techniques for continuous-time sigmadelta modulators. IEEE Trans Circ Syst I 55:3480–3487

    MathSciNet  Google Scholar 

  273. Philips KJP (2005) ΣΔ AD conversion for signal conditioning. Ph.D. thesis Technical University Eindhoven

    Google Scholar 

  274. Philips K, Nuijten PACM, Roovers RLJ, van Roermund AHM, Chavero FM, Pallares MT, Torralba A (2004) A continuous-time SD ADC with increased immunity to interferers. IEEE J Solid-State Circ 39:2170–2178

    Google Scholar 

  275. Nguyen K, Adams R, Sweetland K, Chen H (2005) A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio. IEEE J Solid-State Circ 40:2408–2415

    Google Scholar 

  276. Shettigar P, Pavan S (2012) A 15mW 3.6GS/s CT-SD ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS. In: International solid-state circuits conference, digest of technical papers, pp 156–157

    Google Scholar 

  277. Bolatkale M, Breems LJ, Rutten R, Makinwa KAA (2011) A 4 GHz continuous-time ADC with 70 dB DR and 74 dBFS THD in 125 MHz BW. IEEE J Solid-State Circ 46:2857–2868

    Google Scholar 

  278. Shibata1 H, Schreier R, Yang W, Shaikh A, Paterson D, Caldwell1 T, Alldred D, Lai PW (2012) A DC-to-1GHz tunable RF SD ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz Using 550mW. In: IEEE international solid-state circuits conference, digest of technical papers, pp 150–151

    Google Scholar 

  279. Adams RW (1986) Design and implementation of an audio 18-bit analog-to-digital converter using oversampling techniques. J. Audio Eng Soc 34:153–166

    Google Scholar 

  280. van Veldhoven RHM, Minnis BJ, Hegt HA, van Roermund AHM (2002) A 3.3-mW ΣΔ modulator for UMTS in 0.18-μm CMOS with 70-dB dynamic range in 2-MHz bandwidth. IEEE J Solid-State Circ 37:1645–1652

    Google Scholar 

  281. Lipshitz SP, Vanderkooy J (2001) Why 1-bit sigma-delta conversion is unsuitable for high-quality applications. In: Paper 5395 in 110th convention of the audio engineering society, Amsterdam

    Google Scholar 

  282. Silva PGR, Breems LJ, Makinwa K, Roovers R, Huijsing JH (2007) An IF-to-baseband ΣΔ modulator for AM/FM/IBOC radio receivers with a 118 dB dynamic range. IEEE J Solid-State Circ 42:1076–1089

    Google Scholar 

  283. 292 Ouzounov SF, Roza E, Hegt JA, van de Weide G, van Roermund AHM (2006) Analysis and design of high-performance asynchronous sigma delta modulators with binary quantizer. IEEE J Solid-State Circ 41:588–596

    Google Scholar 

  284. Park H, Nam KY, Su DK, Vleugels K, Wooley BA (2009) A 0.7-V 870-μW digital-audio CMOS sigma-delta modulator. IEEE J Solid-State Circ 44:1078–1088

    Google Scholar 

  285. Engelen J, van de Plassche R, Stikoort E, Venes A (1999) A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF. IEEE J Solid-State Circ 34:1753–1764

    Google Scholar 

  286. Schreier R, Abaskharoun N, Shibata H, Mehr I, Rose S, Paterson D (2006) A 375mW quadrature bandpass delta sigma ADC with 90dB DR and 8.5MHz BW at 44MHz. In: International solid-state circuits conference, digest of technical papers, pp 141–142

    Google Scholar 

  287. Ryckaert J et al (2009) A 2.4GHz Low-Power Sixth-Order RF bandpass SD Converter in CMOS. IEEE J Solid-State Circ 44:2873–2880

    Google Scholar 

  288. 289 Harrison J, Nesselroth M, Mamuad R, Behzad A, Adams A, Avery S (2012) An LC bandpass SD ADC with 70dB SNDR over 20MHz bandwidth using CMOS DACs. In: International solid-state circuits conference, digest of technical papers, pp 146–147

    Google Scholar 

  289. Chae H, Jeong J, Manganaro G, Flynn M (2012) A 12mW low-power continuous-time bandpass SD modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF. In: International solid-state circuits conference, digest of technical papers, pp 148–149

    Google Scholar 

  290. van der Zwan EJ, Philips K, Bastiaansen CAA (2000) A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system for AM/FM radio receivers. IEEE J Solid-State Circ 35:1810–1819

    Google Scholar 

  291. Bergveld HJ, van Kaam KMM, Leenaerts DMW, Philips KJP, Vaassen AWP, Wetzker G (2004) A low-power highly-digitized receiver for 2.4-GHz-band GFSK applications. In: IEEE radio frequency integrated circuits (RFIC) symposium, pp 347–350

    Google Scholar 

  292. 283 van Veldhoven RHM (2003) A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/ CDMA2000/UMTS receiver. IEEE J Solid-State Circ 38:2069–2076

    Google Scholar 

  293. Kavusi S, Kakavand H, El Gamal A (2006) On incremental sigma-delta modulation with optimal filtering. IEEE Trans Circ Syst I: Fundam Theor Appl 53:1004–1015

    MathSciNet  Google Scholar 

  294. Irons FH (2000) The noise power ratio theory and adc testing. IEEE Trans Instrum Meas 49:659–665

    Google Scholar 

  295. Milor LS (1998) A tutorial introduction to research on analog and mixed-signal circuit testing. IEEE Trans Circ Syst-II 45:1389–1407

    Google Scholar 

  296. Veendrick H (1998) Deep submicron CMOS ICs. Kluwer, Deventer. ISBN: 90-557-612-81 (Revised edition: H. Veendrick, Nanometer CMOS ICs, Springer, Deventer ISBN: 978-1-4020-8332-7, 2008)

    Google Scholar 

  297. Langevelde Rv (2003) RF performance and modeling of CMOS devices. In: Educational sessions workbook of custom integrated circuits conference

    Google Scholar 

  298. Pelgrom MJM, Vertregt M (1997) CMOS technology for mixed signal ICs. Solid-State Electron 41:967–974

    Google Scholar 

  299. Gregor RW (1992) On the relationship between topography and transistor matching in an analog CMOS technology. IEEE Trans Electron Devices 39:275–282

    Google Scholar 

  300. Stathis JH, Zafar S (2006) The negative bias temperature instability in MOS devices: a review. Microelectron Reliab 46:270–286

    Google Scholar 

  301. Hook TB, Brown J, Cottrell P, Adler E, Hoyniak D, Johnson J, Mann R (2003) Lateral ion implant straggle and mask proximity effect. IEEE Trans Electron Devices 50:1946–1951

    Google Scholar 

  302. Drennan P, Kniffin M, Locascio D (2006) Implications of proximity effects for analog design. In: IEEE custom integrated circuits conference, pp 169–176

    Google Scholar 

  303. Bianchi RA, Bouche G, Roux-dit-Buisson O (2002) Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance. In: Technical digest international electron devices meeting, pp 117–120

    Google Scholar 

  304. Su K-Wi et al (2003) A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics. In: Proceedings of the IEEE custom integrated circuits conference, pp 245–248

    Google Scholar 

  305. Wils N, Tuinhout HP, Meijer M (2009) Characterization of STI edge effects on CMOS variability. IEEE Trans Semiconductor Manufacturing 22:59–65

    Google Scholar 

  306. Ge L, Adams V, Loiko K, Tekleab D, Bo X-Z, Foisy M, Kolagunta V, Veeraraghavan S (2007) Modeling and simulation of poly-space effects in uniaxially-strained etch stop layer stressors. In: IEEE international SOI conference, pp 25–26

    Google Scholar 

  307. Tuinhout HP, Pelgrom MJM, Penning de Vries R, Vertregt M (1996) Effects of metal coverage on MOSFET matching. In: Technical digest international electron devices meeting, pp 735–739

    Google Scholar 

  308. Tuinhout HP, Bretveld A, Peters WCM (2004) Measuring the span of stress asymmetries on high-precision matched devices. In: International conference on microelectronic test structures, pp 117–122

    Google Scholar 

  309. Tuinhout HP, Vertregt M (2001) Characterization of systematic MOSFET current factor mismatch caused by metal CMP dummy structures. IEEE Trans Semiconductor Manufacturing 14:302–310

    Google Scholar 

  310. Pelgrom MJM, Vertregt M, Tuinhout HP Matching of MOS transistors. MEAD course material, 1998–2009

    Google Scholar 

  311. Lam M-F, Tammineedi A, Geiger R (2001) Current mirror layout strategies for enhancing matching performance. Analog Integr Circ Signal Process 28:9–26

    Google Scholar 

  312. Tuinhout HP, Elzinga H, Brugman JT, Postma F (1994) Accurate capacitor matching measurements using floating-gate test structures. In: IEEE international conference on microelectronic test structures, pp 133–137

    Google Scholar 

  313. Tuinhout HP, van Rossem F, Wils N (2009) High-precision on-wafer backend capacitor mismatch measurements using a benchtop semiconductor characterization system. In: IEEE international conference on microelectronic test structures, pp 3–8

    Google Scholar 

  314. Drennan PG (1999) Diffused resistor mismatch modeling and characterization. In: Bipolar/BiCMOS circuits and technology meeting, pp 27–30

    Google Scholar 

  315. Tuinhout HP, Hoogzaad G, Vertregt M, Roovers R, Erdmann C (2002) Design and characterisation of a high precision resistor ladder test structure. In: IEEE international conference on microelectronic test structures, pp 223–228

    Google Scholar 

  316. Lakshmikumar KR, Hadaway RA, Copeland MA (1986) Characterization and modeling of mismatch in MOS transistors for precision analog design. IEEE J Solid-State Circ 21: 1057–1066

    Google Scholar 

  317. Michael C, Ismail M (1992) Statistical modeling of device mismatch for analog MOS integrated circuits. IEEE J Solid-State Circ 27:154–166

    Google Scholar 

  318. Forti F, Wright ME (1994) Measurement of MOS current mismatch in the weak inversion region. IEEE J Solid-State Circ 29:138–142

    Google Scholar 

  319. Croon JA, Sansen W, Maes HE (2005) Matching properties of deep sub-micron MOS transistors. Springer, Dordrecht, The Netherlands. ISBN: 0-387-24314-3

    Google Scholar 

  320. Tuinhout HP (2003) Improving BiCMOS technologies using BJT parametric mismatch characterisation. In: Bipolar/BiCMOS circuits and technology meeting, pp 163–170

    Google Scholar 

  321. Brown AR, Roy G, Asenov A (2007) Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture. IEEE Trans Electron Devices 54:3056–3063

    Google Scholar 

  322. Mizuno T, Okamura J, Toriumi A (1994) Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs. IEEE Trans Electron Devices 41:2216–2221

    Google Scholar 

  323. Bastos J, Steyaert M, Roovers R, Kinget P, Sansen W, Graindourze B, Pergoot A, Janssens E (1995) Mismatch characterization of small size MOS transistors. In: IEEE international conference on microelectronic test structures, pp 271–276

    Google Scholar 

  324. Stolk PA, Widdershoven FP, Klaassen DBM (1998) Modeling statistical dopant fluctuations in MOS transistors. IEEE Trans Electron Devices 45:1960–1971

    Google Scholar 

  325. Andricciola P, Tuinhout HP (2009) The temperature dependence of mismatch in deep-submicrometer bulk MOSFETs. IEEE Electron Device Lett 30:690–692

    Google Scholar 

  326. Hook TB, Johnson JB, Cathignol A, Cros A, Ghibaudo G (2011) Comment on (channel length and threshold voltage dependence of a transistor mismatch in a 32-nm HKMG technology). IEEE Trans Electron Devices 58:1255–1256

    Google Scholar 

  327. Croon JA, Tuinhout HP, Difrenza R, Knol J, Moonen AJ, Decoutere S, Maes HE, Sansen W (2002) A comparison of extraction techniques for threshold voltage mismatch. In: IEEE international conference on microelectronic test structures, pp 235–240

    Google Scholar 

  328. Tuinhout HP (2005) Electrical characterisation of matched pairs for evaluation of integrated circuit technologies. Ph.D. Thesis Delft University of Technology. (http://repository.tudelft.nl/file/82893/025295)

  329. Takeuchi K, Hane M (2008) Statistical compact model parameter extraction by direct fitting to variations. IEEE Trans Electron Devices 55:1487–1493

    Google Scholar 

  330. Cheng B, Roy S, Asenov A (2007) Statistical compact model parameter extraction strategy for intrinsic parameter fluctuation. In: Grasser T, Selberherr S (eds) Simulation on semiconductor processes and devices. Springer, Wien, pp 301–304

    Google Scholar 

  331. Vertregt M, Scholtens PCS (2004) Assessment of the merits of CMOS technology scaling for analog circuit design. In: 30th European solid-state circuits conference, pp 57–64

    Google Scholar 

  332. Pelgrom MJM (1994) Low-power high-speed A/D conversion. In: 20th European solid-state circuits conference, low-power workshop

    Google Scholar 

  333. Kinget P, Steyaert M (1996) Impact of transistor mismatch on the speed accuracy power trade-off. In: Custom integrated circuits conference

    Google Scholar 

  334. Pelgrom MJM, Tuinhout HP, Vertregt M (1998) Transistor matching in analog CMOS applications. In: International electron devices meeting, pp 915–918

    Google Scholar 

  335. Doorn TS, ter Maten EJW, Croon JA, Di Bucchianico A, Wittich O (2008) Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield. In: 34th European solid-state circuits conference, pp 230–233

    Google Scholar 

  336. Dijkstra E, Nys O, Blumenkrantz E (1995) Low power oversampled A/D converters. In: van de Plassche RJ (ed) Advances in analog circuit design. Kluwer Academic Publishers, Norwell, p 89

    Google Scholar 

  337. Pelgrom MJM (1998) Low-power CMOS data conversion. In: Sanchez-Sinencio E, Andreou A (eds) Low-voltage low-power integrated circutis and systems. IEEE Press, New York. ISBN: 0-7803-3446-9

    Google Scholar 

  338. Walden RH (1999) Analog-to-digital converter survey and analysis. IEEE J Select Areas in Commun 17:539–550

    Google Scholar 

  339. Vittoz E (1995) Low power low-voltage limitations and prospects in analog design. In: van de Plassche RJ (ed) Advances in analog circuit design. Kluwer Academic Publishers, Norwell, p 3

    Google Scholar 

  340. Giotta D, Pessl P, Clara M, Klatzer W, Gaggl R (2004) Low-power 14-bit current steering DAC for ADSL applications in 0.13 μm CMOS. In: European solid-state circuits conference, pp 163–166

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Pelgrom, M.J.M. (2013). Characterization and Specification. In: Analog-to-Digital Conversion. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1371-4_10

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-1371-4_10

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-1370-7

  • Online ISBN: 978-1-4614-1371-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics