Functional Test Compaction

  • Mingsong Chen
  • Xiaoke Qin
  • Heon-Mo Koo
  • Prabhat Mishra
Chapter

Abstract

Validation of System-on-Chip designs involves huge amounts of functional test data. A lot of test compaction techniques have been proposed in manufacturing test domain because they have a significant impact on overall testing cost and time. However, there is limited progress in functional test compaction in validation domain because functional tests are considered as one-time effort in design methodology. Nevertheless, millions of tests are used in the current industrial practice, and regression testing is conducted regularly during design cycle. Therefore, reduction in functional tests will have significant impact on overall design effort by removing redundant tests as well as selecting effective tests. This chapter presents an efficient test compaction technique to reduce the functional test set.

Keywords

Compaction 

References

  1. 1.
    Barnhart C, Brunkhorst V, Distler F, Farnsworth O, Ferko A, Keller B, Scott D, Koenemann B, Onodera T (2002) Expending OP-MISR beyond 10x scan test efficiency. IEEE Des Test Comput 19(5):65–73Google Scholar
  2. 2.
    Campenhout D, Mudge T, Hayes J (1999) High-level test generation for design verification of pipelined microprocessors. In: Proceedings of design automation conference (DAC), pp 185–188Google Scholar
  3. 3.
    Chandra A, Chakrabarty K (2001) System-on-a-Chip test data compression and decompression architectures based on golomb codes. IEEE Trans Comput Aided Des Integr Circuits Syst 20(3):355–368Google Scholar
  4. 4.
    Chandra A, Chakrabarty K (2003) Test data compression and dtest resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Trans Comput 52(8):1076–1088Google Scholar
  5. 5.
    Cheng K, Krishnakumar S (1996) Automatic generation of functional vectors using the extended finite state machine model. ACM Trans Des Autom Electron Syst 1(1):57–79Google Scholar
  6. 6.
    Corno F, Prinetto P, Rebaudengo M, Reorda M (1997) New static compaction techniques of test sequences for sequential circuits. In: Proceedings of European conference on design and test (ED&TC), pp 37–43Google Scholar
  7. 7.
    Dimopoulos M, Linardis P (2004) Efficient static compaction of test sequence sets through the application of set covering techniques. In: Proceedings of design automation and test in Europe (DATE), pp 194–199Google Scholar
  8. 8.
    El-Maleh A, Osais Y (2003) Test vector decomposition-based static compaction algorithms for combinational circuits. ACM Trans Des Autom Electron Syst 8(4):430–459Google Scholar
  9. 9.
    El-Maleh A, Al-Suwaiyan A (2001) An efficient test relaxation technique for combinational and full-scan sequential circuits. In: Proceedings of VLSI test symposium (VTS), pp 53–59Google Scholar
  10. 10.
    Flores P, Neto H, Marques-Silva J (1999) On applying set covering models to test set compaction. In: Proceedings of Great Lakes symposium on VLSI (GLSVLSI), pp 8–11Google Scholar
  11. 11.
    Gonciari P, Nicolici N (2003) Variable-length input Huffman coding for system-on-a-chip test. IEEE Trans Comput Aided Des Integr Circuits Syst 22(6):783–796Google Scholar
  12. 12.
    Hennessy J, Patterson D (2003) Computer architecture: a quantitative approach. Morgan Kaufmann, San FransiscoGoogle Scholar
  13. 13.
    Ho R, Yang C, Horowitz M, Dill D (1995) Architecture validation for processors. In: Proceedings of international symposium on computer architecture (ISCA), pp 404–413Google Scholar
  14. 14.
    Hochbaum D (1996) An optimal test compression procedure for combinational circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 15(10):1294–1299Google Scholar
  15. 15.
    Jas A, Touba N (1998) Test vector compression via cyclical scan chains and its application to testing core-based designs. In: Proceedings of international test conference (ITC), pp 458–464Google Scholar
  16. 16.
    Jas A, Ghosh-Dastidar J, Mom-Eng N, Touba N (2003) An efficient test vector compression scheme using selective Huffman coding. IEEE Trans Comput Aided Des Integr Circuits Syst 22(6):797–806Google Scholar
  17. 17.
    Koo H, Mishra P (2008) Specification-based compaction of directed tests for functional validation of pipelined processors. In: Proceedings of international symposium on hardware/software codesign and system synthesis (CODES + ISSS), pp 137–142Google Scholar
  18. 18.
    Krishna C, Jas A, Touba N (2001) Test vector encoding using partial LFSR reseeding. In: Proceedings of international test conference (ITC), pp 885–893Google Scholar
  19. 19.
    Li L, Chakrabarty K, Touba N (2003) Test data compression using dictionaries with selective entries and fixed-length indices. ACM Trans Des Autom Electron Syst 8(4):470–490Google Scholar
  20. 20.
    Moundanos D, Abraham J, Hoskote Y (1998) Abstraction techniques for validation coverage analysis and test generation. IEEE Trans Comput 47(1):2–13CrossRefGoogle Scholar
  21. 21.
    Miyase K, Kajihara S, Reddy S (2002) A method of static test compaction based on don’t care identification. In: Proceedings of international workshop on electronic design, test, and application (ITC), pp 392–395Google Scholar
  22. 22.
    Pomeranz I, Reddy S (2001) Forward-looking fault simulation for improved static compaction. IEEE Trans Comput Aided Des Integr Circuits Syst 20(10):189–194Google Scholar
  23. 23.
    Pomeranz I, Reddy S (2010) On test generation with test vector improvement. IEEE Trans Comput Aided Des Integr Circuits Syst 29(3):502–506Google Scholar
  24. 24.
    Rajski J, Tyszer J, Kassab M, Mukherjee N (2004) Embedded deterministic test. IEEE Trans Comput Aided Des Integr Circuits Syst 23(5):776–792Google Scholar
  25. 25.
    Reda S, Orailoglu A (2002) Reducing test application time through test data mutation encoding. In: Proceedings of design automation and test in Europe (DATE), pp 387–393Google Scholar
  26. 26.
    Reddy S, Miyase K, Kajihara S, Pomeranz I (2002) On test data volume reduction for multiple scan chain designs. In: Proceedings of VLSI test symposium (VTS), pp 103–108Google Scholar
  27. 27.
    Rudnick E, Patel J (1999) Efficient techniques for dynamic test sequence compaction. IEEE Comput Soc 48(3):323–330Google Scholar
  28. 28.
    Shen J, Abraham J (2000) An RTL abstraction technique for processor microarchitecture validation and test generation. J Electron Test Theory Appl 16(1):67–81Google Scholar
  29. 29.
    Touba N (2006) Survey of test vector compression techniques. IEEE Des Test Comput 23(4):294–303Google Scholar
  30. 30.
    Utamaphethai N, Blanton R, Shen J (2000) Effectiveness of microarchitecture test program generation. IEEE Des Test Comput 17(4):38–49Google Scholar
  31. 31.
    Venkatesh R, Shanmugasundaram P, Parekhji R (2011) An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. In: Proceedings of VLSI test symposium (VTS), pp 285–290Google Scholar
  32. 32.
    Villa T, Kam T, Brayton R, Sangiovanni-Vincenteili A (1997) Explicit and implicit algorithms for binate covering problems. IEEE Trans Comput Aided Des Integr Circuits Syst 16(7):677–691Google Scholar
  33. 33.
    Wang L, Wen X, Wu S, Wang Z, Jiang Z, Sheu B, Gu X (2008) VirtualScan: test compression technology using combinational logic and one-pass ATPG. IEEE Des Test Comput 25(2):122–130Google Scholar
  34. 34.
    Wang Z, Chakrabarty K (2005) Test data compression for IP embeded cores using selective encoding of scan slices. In: Proceedings of international test conference (ITC), pp 581–590Google Scholar
  35. 35.
    Wohl P, Waicukauski A, Patel S, DaSilva F, Williams T, Kapur R (2005) Efficient compression of deterministic patterns into multiple PRPG seeds. In: Proceedings of international test conference (ITC), paper 36.1Google Scholar
  36. 36.
    Wurtenberger A, Tautermann C, Hellebrand S (2004) Data compression for multiple scan chains using dictionaries with corrections. In: Proceedings of international test conference (ITC), pp 926–935Google Scholar
  37. 37.
    Zhang Y, Wang D, Wang J, Zheng W (2005) Using model-based test program generator for simulation validation. In: Proceedings of international conference on embedded software and systems, pp 549–556Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Mingsong Chen
    • 1
  • Xiaoke Qin
    • 2
  • Heon-Mo Koo
    • 3
  • Prabhat Mishra
    • 2
  1. 1.Software Engineering InstituteEast China Normal UniversityShanghaiPeople’s Republic of China
  2. 2.Department of Computer and Information Science and EngineeringUniversity of FloridaGainsvilleUSA
  3. 3.Intel corporationSantaUSA

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