Abstract
Transaction-level modeling (TLM) is widely used to enable early exploration for both hardware and software designs. It can reduce the overall design and validation effort of complex system-on-chip (SoC) architectures. However, due to lack of automated techniques coupled with limited reuse of validation efforts between different abstraction levels, SoC validation is becoming a major bottleneck. This chapter presents a novel top-down methodology for automatically generating register transfer level (RTL) tests from TLM tests. Case studies using a router example and a 64-bit Alpha AXP pipelined processor demonstrate that the presented approach can achieve intended functional coverage of the RTL designs as well as can capture various functional errors and inconsistencies between specifications and implementations.
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Chen, M., Qin, X., Koo, HM., Mishra, P. (2013). Reuse of System-Level Validation Efforts. In: System-Level Validation. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1359-2_12
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DOI: https://doi.org/10.1007/978-1-4614-1359-2_12
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