Abstract
Processors with multiple cores and complex cache coherence protocols are widely employed to improve the overall performance. It is a major challenge to verify the correctness of a cache coherence protocol since the number of reachable states grows exponentially with the number of cores. This chapter describes an efficient test generation technique, which can be used to achieve full state and transition coverage in simulation-based verification for a wide variety of cache coherence protocols. Based on effective analysis of the state space structure, this method can generate more efficient test sequences compared with tests generated by breadth first search. Moreover, this approach can generate tests on-the-fly due to its space efficient design.
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Notes
- 1.
In this chapter, we use the term “core” to refer to each single processing units in multicore or multiprocessor systems.
- 2.
There are many transitions that start and end in the same states. For example, the global state will not change if a core in S state issues a load operation. Usually, these transitions are easier to cover, because they can be activated by appending one more operation at the end of existing tests, which are used to activate corresponding initial states. As a result, they are omitted in the state space structure description in this section. However, all possible transitions are considered in the actual implementation of TGTC as well as in the experimental results.
- 3.
A global exclusive state is a global state with a cache block in exclusive state (e.g., IIE, IEI, and EII in Fig. 11.4).
- 4.
A global owned state is a global state with a cache block in owned state (e.g., IOI, IOS,..., OSS in Fig. 11.5).
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Chen, M., Qin, X., Koo, HM., Mishra, P. (2013). Test Generation for Cache Coherence Validation. In: System-Level Validation. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1359-2_11
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