Advertisement

Proposed Multiplication Algorithm for DKF

Chapter
  • 1k Downloads
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 118)

Abstract

An efficient and low-power multiplication algorithm has been proposed in this chapter. It reduces the number of add operations during multiplication by rounding any sequence of 1s in the fractional part. The impact of using the proposed multiplication method on FIR and IIR filters response has been studied. Experimental results show that the proposed algorithm achieves up to 17% power saving and 16% increasing in speed, with only 1% accuracy loss compared to Horner’s algorithm. The new multiplication method has been validated experimentally using the eZ430-RF2500 wireless sensor board. In the next chapter, we will study the impact of using the proposed multiplication method on the power consumption of the proposed DKF.

Keywords

Sensor Node Wireless Sensor Network Finite Impulse Response Partial Product Infinite Impulse Response 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Bibliography

  1. 1.
  2. 2.
    J. Polastre, R. Szewczyk, and D. Culler, “Telos: enabling ultra-low power wireless research,” in Proceeding of the Information Processing in Sensor Networks, pp. 364–369, November 2005.Google Scholar
  3. 3.
    H.T. Nguyen and A. Chattejee, “Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis,” IEEE Transactions on Very Large Scale Integration Systems, vol. 8, pp. 419–424, May 2000.CrossRefGoogle Scholar
  4. 4.
    K. Venkat and M. Raju, “Efficient Signal Conditioning for Microcontroller Based Medical Solutions,” in Proceeding of the IEEE International Symposium on Consumer Electronics, Dallas, Texas, USA, June 2007, pp. 1–5.Google Scholar
  5. 5.
    R. Tamura, M. Honma, N. Togawa, M. Yanagisawa, T. Ohtsuki, and M. Satoh, “FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm,” in Proceeding of the IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, December 2008, pp. 701–704.Google Scholar
  6. 6.
    R. Landry, Jr., V. Calmettes, and E. Robin, “High speed IIR filter for XILINX FPGA,” in Proceeding of the Midwest Symposium on Circuits and Systems, Notre Dame, Indian, USA, August 1998, pp. 46–49.Google Scholar
  7. 7.
    Texas Instruments Inc., “MSP430 family of microcontrollers,” http://www.ti.com/msp430.
  8. 8.
    A. Abdelgawad, S. Abdelhak, S. Ghosh, and M. Bayoumi, “A low-power multiplication algorithm for signal processing in wireless sensor networks,” in Proceeding of the 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, Mexico, August 2009, pp. 695–698.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.Essex JunctionUSA
  2. 2.University of Louisiana at LafayetteLafayetteUSA

Personalised recommendations