Skip to main content

Introduction to Interconnects

  • Chapter
Low Power Interconnect Design
  • 1118 Accesses

Abstract

Due to the importance of interconnects in current and future ICs, significant research is going on over the past two decades, covering different areas such as parasitic extraction, interconnect models, and interconnect design methodologies. In this chapter, a brief review of the background of on-chip electrical interconnect is provided. In Sect. 1.1, a typical design flow for application-specific integrated circuits (ASICs) is described. Challenges in DSM technologies due to interconnect dominant behavior are discussed. In Sect. 1.2, different design criteria that need to be considered during the interconnect design procedure are described. The impedance characteristics of interconnect are presented in Sect. 1.3; specially, the resistance, capacitance, and inductance. Interconnect characteristics, models, and design methodologies are reviewed in Sects. 1.4, 1.5, and 1.6, respectively. Finally, some conclusions are offered in Sect. 1.7.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. H. Veendrick, Deep Submicron CMOS ICs - From Basics to ASICs. Deventer, Netherlands: Kluwer, 1998.

    Google Scholar 

  2. Tiri, Kris, and Ingrid Verbauwhede. “A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation.” Proceedings of the conference on Design, automation and test in Europe-Volume 1. IEEE Computer Society, 2004.

    Google Scholar 

  3. Rabaey, Jan M., and Massoud Pedram. Low Power Design Methodology. Vol. 1. Kluwer academic publishers, 1996.

    Google Scholar 

  4. P. Ghosh, R. Mangaser, K. Rose, “Interconnect-dominated VLSI design”, Proceedings of the Conference on Advanced Research, March 1999, pp. 114–122.

    Google Scholar 

  5. Semiconductor Industry Association, The National Technology Roadmap for Semiconductors - 1997 Edition.

    Google Scholar 

  6. M. T. Bohr, Proc. IEEE International Electron Devices Meeting, p. 241, 1995.

    Google Scholar 

  7. Davidson, Evan E. “Large chip vs. MCM for a high-performance system.” Micro, IEEE 18.4 (1998): 33–41.

    Google Scholar 

  8. Shigyo, Naoyuki. “Tradeoff between interconnect capacitance and RC delay variations induced by process fluctuations.” Electron Devices, IEEE Transactions on 47.9 (2000): 1740–1744.

    Article  Google Scholar 

  9. Banerjee, Kaustav, and Amit Mehrotra. “Inductance aware interconnect scaling.” Quality Electronic Design, 2002. Proceedings. International Symposium on. IEEE, 2002.

    Google Scholar 

  10. Rajit Chandra, “Accurate models vital for Signal Integrity verification.”

    Google Scholar 

  11. Davis, Jeffrey A., and James D. Meindl. “Compact distributed RLC interconnect models-Part I: Single line transient, time delay, and overshoot expressions.” IEEE Transactions on Electron Devices 47.11 (2000): 2068–2077.

    Article  Google Scholar 

  12. Davis, Jeffrey A., and James D. Meindl. “Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks.” Electron Devices, IEEE Transactions on 47.11 (2000): 2078–2087.

    Article  Google Scholar 

  13. Bruckstein, A. M., and T. Kailath. “Inverse scattering for discrete transmission-line models.” SIAM review 29.3 (1987): 359–389.

    Article  MATH  MathSciNet  Google Scholar 

  14. Okamoto, Takumi, and Jason Cong. “Buffered Steiner tree construction with wire sizing for interconnect layout optimization.” Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design. IEEE Computer Society, 1997.

    Google Scholar 

  15. Robins, Gabriel, and Alexander Zelikovsky. “Improved Steiner tree approximation in graphs.” SODA. 2000.

    Google Scholar 

  16. Philipossian, Ara, and Scott Olsen. “Fundamental tribological and removal rate studies of inter-layer dielectric chemical mechanical planarization.” Japanese journal of applied physics 42.10R (2003): 6371.

    Google Scholar 

  17. Kloster, Grant M., et al. “Method of forming a selectively converted inter-layer dielectric using a porogen material.” U.S. Patent No. 7,018,918. 28 Mar. 2006.

    Google Scholar 

  18. Alpert, Charles J., Anirudh Devgan, and Stephen T. Quay. “Is wire tapering worthwhile?.” Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design. IEEE Press, 1999.

    Google Scholar 

  19. Ismail, Yehea I., and Eby G. Friedman. “Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 8.2 (2000): 195–206.

    Google Scholar 

  20. Venkatesan, Raguraman, Jeffrey A. Davis, and James D. Meindl. “Compact distributed RLC interconnect models-part IV: unified models for time delay, crosstalk, and repeater insertion.” Electron Devices, IEEE Transactions on 50.4 (2003): 1094–1102.

    Article  Google Scholar 

  21. Gupta, Rohini, Bogdan Tutuianu, and Lawrence T. Pileggi. “The Elmore delay as a bound for RC trees with generalized input signals.” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 16.1 (1997): 95–104.

    Article  Google Scholar 

  22. Chandrakasan, A. P., S. Sheng, and R. W. Brodersen, “Low-power Digital CMOS Design,” IEEE Journal of Solid State Circuits, pp. 473–484, April 1992.

    Google Scholar 

  23. P. Saxena and N. Menezes and P. Cocchini and D.A. Kirkpatrick, “Repeater scaling and its impact on CAD,” IEEE Transactions on Computer-Aided Design, vol. 23, no. 4, pp. 451–463, 2004.

    Article  Google Scholar 

  24. P.J. Osler, “Placement driven synthesis case studies on two sets of two chips: hierarchical and flat,” in Proceedings of International Symposium on Physical Design, San Diego, California, 2004, pp. 190–197.

    Google Scholar 

  25. Okamoto, Takumi, and Jason Cong. “Buffered Steiner tree construction with wire sizing for interconnect layout optimization.” Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design. IEEE Computer Society, 1997.

    Google Scholar 

  26. Van Ginneken, Lukas PPP. “Buffer placement in distributed RC-tree networks for minimal Elmore delay.” Circuits and Systems, 1990., IEEE International Symposium on. IEEE, 1990.

    Google Scholar 

  27. Morrison, Ralph. Grounding and shielding techniques. Wiley, 1998.

    Google Scholar 

  28. Siah, Eng Swee, et al. “Coupling studies and shielding techniques for electromagnetic penetration through apertures on complex cavities and vehicular platforms.” Electromagnetic Compatibility, IEEE Transactions on 45.2 (2003): 245–257.

    Google Scholar 

  29. Moiseev, Konstantin, Shmuel Wimer, and Avinoam Kolodny. “Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.” Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on. IEEE, 2006.

    Google Scholar 

  30. Yu, Hao, and Lei He. “Staggered twisted-bundle interconnect for crosstalk and delay reduction.” Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on. IEEE, 2005.

    Google Scholar 

  31. Soudan, Bassel. “Reducing inductive coupling skew in wide global signal busses.” Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on. IEEE, 2006.

    Google Scholar 

  32. Rabaey, Jan M., Anantha P. Chandrakasan, and Borivoje Nikolic. Digital integrated circuits. Vol. 2. Englewood Cliffs: Prentice hall, 2002.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer Science+Business Media New York

About this chapter

Cite this chapter

Saini, S. (2015). Introduction to Interconnects. In: Low Power Interconnect Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1323-3_1

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-1323-3_1

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-1322-6

  • Online ISBN: 978-1-4614-1323-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics