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Power Package Typical Assembly Process

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Power Electronic Packaging
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Abstract

Assembly manufacturing processes can be broken into front of line (FOL) and end of line (EOL) components, each having several process steps.

In FOL, typical processes include the wafer handling process, die pickup from tape that becomes more of a problem as die thinning becomes more extreme. FOL die attach processes can induce residual stresses due to process shrinkage and CTE mismatch. Wire bonding processes can induce bond pad cratering or failure in the device under bond pad. In EOL, typical processes include molding process with curing stress and residual stress, molding ejection, and clamping process that can potentially cause cracking in molding compound, trim and form and singulation process that would induce the stress wave to crack the die or the EMC. Before the actual assembly process, the virtual modeling and analysis is very important to find out the optimized solution and failure mode which can extremely benefit to enhance the quality and reliability of the power packaging, especially for new product development.

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References

  1. Reiche M, Wagner G (2003) Wafer thinning: techniques for ultra-thin wafers. Adv Packag 12(3):29

    Google Scholar 

  2. Liu Y, Desbins D, Irving S et al (2006) Systematic evaluation of die thinning application in a power SIP by simulation. In: Proceedings of 56th electronic components and technology conference, San Diego

    Google Scholar 

  3. Timoshenko S, Woinowsky-Krieger S (1959) Theory of plates and shells. McGraw-Hill, New York

    Google Scholar 

  4. Wu E (2003) Influence of grinding process on semiconductor chip strength. In: Proceedings of 53th electronic components and technology conference, New Orleans

    Google Scholar 

  5. Yeh C, Zhou W (1996) Parametric finite element analysis of flip chip reliability. Int J Microcirc Electron Packag 19(2):120–127

    Google Scholar 

  6. Yu S, Xu Q (1996) Structural mechanics and manufacturing mechanics in electronic packaging. In: Proceedings of the 2nd international symposium on electronic packaging technology, Shanghai, Dec 1996, pp 120–124

    Google Scholar 

  7. Wang J, Qian Z, Liu S (1998) Process induced stresses of a flip-chip packaging by sequential processing modeling technique. ASME J Electron Packag 120:309–313

    Article  Google Scholar 

  8. Mannan SH et al (2000) Solder paste reflow modeling for flip chip assembly. In: 3rd Electronics packaging technology conference, sheraton towers, Singapore, Dec 2000, pp 103–109

    Google Scholar 

  9. Liu Y, Antes H (1999) An improved implicit algorithm for the elastic viscoplastic boundary element method. Z Angew Math Mech 79:317–333

    Article  MathSciNet  MATH  Google Scholar 

  10. Paulino GH, Liu Y (2001) Implicit consistent and continuum tangent operators in elastoplastic boundary element formulations. Comput Meth Appl Mech Eng 190:2157–2179

    Article  MATH  Google Scholar 

  11. Maniatty AM, Liu Y, Ottmar K et al (2001) Stabilized finite element method for viscoplastic flow: formulation and a simple progressive solution strategy. Comput Meth Appl Mech Eng 190:4609–4625

    Article  MATH  Google Scholar 

  12. Simo JC, Hughes TJR (1997) Computational inelasticity. Springer, New York, pp 114–151

    Google Scholar 

  13. Qian Z, Liu S (1999) A damage coupling framework of unified viscoplasticity for the fatigue of solder alloys. ASME J Electron Packag 121:162–168

    Article  Google Scholar 

  14. Feustel F, Wiese S, Meusel E (2000) Time-dependent material modeling for finite element analyses of flip chips. In: Proceedings of 50th electronic components and technology conference, Las Vegas, NV, May 2000, pp 1548–1553

    Google Scholar 

  15. Brown SB, Kim KH, Anand L (1989) An internal variable constitutive model for hot working of metals. Int J Plast 5:95–130

    Article  MATH  Google Scholar 

  16. Liu Y, Irving S, Tumulak M, Elsie A (2002) Assembly process induced stress analysis for new FLMP package by 3D FEA. In: Proceedings of 52th electronic components and technology conference, San Diego

    Google Scholar 

  17. Liu Y, Irving S, Luk T (2008) Thermosonic wire bonding process simulation and bond pad over active stress analysis. IEEE Trans Electron Packag Manuf 31:61–71

    Article  Google Scholar 

  18. Harman G (2010) Wire bonding in microelectronics, 3rd edn. McGraw-Hill, New York

    Google Scholar 

  19. Ikeda T, Miyazaki N, Kudo K et al (1999) Failure estimation of semiconductor chip during wire bonding process. ASME J Electron Packag 121:85–91

    Article  Google Scholar 

  20. Qian Q, Liu Y, Luk T, Irving S (2008) Wire bonding capillary profile and bonding process parameter optimization simulation. In: International conference on thermal, mechanical and multi-physics simulation and experiments in microelectronics and micro-systems, EuroSimE 2008, Freiburg, Germany

    Google Scholar 

  21. Mayer M, Paul O, Bolliger D, Baltes H (1999) Integrated temperature microsensores for characterization and optimization of thermosonic ball bonding process. In: Proceedings of 49th electronic components and technology conference, San Diego, California, May 1999, pp 463–468

    Google Scholar 

  22. Levine L (1995) The ultrasonic wedge bonding mechanism: two theories converge. In: Proceedings of the international symposium on microelectronics. ISHM, Los Angeles, California, 24–26 Oct 1995, pp 242–246

    Google Scholar 

  23. Liu YM, Liu Y, Irving S et al (2006) Optimization of 2 mil Al wire wedge bond of D-Pak. In: ICEPT7, Shanghai, 26–29 Aug 2006

    Google Scholar 

  24. Bird RB, Armstrong RC, Hassager O (1987) Dynamics of polymeric liquids, vol 1. Wiley, New York

    Google Scholar 

  25. Han S, Wang KK (2000) Flow analysis in a chip cavity during semiconductor encapsulation. Trans ASME J Electron Packag 122:160–167

    Article  Google Scholar 

  26. Lee TK et al (2008) Some case studies on air venting analysis of semiconductor package using moldflow. In: EPTC 2008, Singapore, pp 444–449 (© 2008 IEEE. Reprinted with permission from IEEE)

    Google Scholar 

  27. Liu Y, Irving S, Desbien D, Luk T (2006) Simulation and analysis for typical package assembly manufacture. In: EuroSimE 2006, Como, Italy

    Google Scholar 

  28. Irving S, Liu Y (2005) An effective method for improving IC package die failure during assembly punch processing. In: Proceedings of the 6th international conference on thermal, mechanical and multi-physics simulation and experiments in micro-electronics and micro-systems—EuroSimE 2005, Berlin, Germany

    Google Scholar 

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Liu, Y. (2012). Power Package Typical Assembly Process. In: Power Electronic Packaging. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1053-9_8

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  • DOI: https://doi.org/10.1007/978-1-4614-1053-9_8

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