Multi-net Sizing and Spacing of Bundle Wires

  • Konstantin Moiseev
  • Avinoam Kolodny
  • Shmuel Wimer
Chapter

Abstract

At this point, we move from net-by-net optimization to simultaneous optimization of multiple nets. The description of multi-net optimization algorithms begins from considering a simple structure – a bundle of equal-length parallel wires. The methods described in this chapter will be generalized in the next chapter for more general layouts.

Keywords

Migration Blindness Metrics Metrics 

References

  1. [Boyd 07]
    Boyd, S., Kim, S. J., Vandenberghe, L., & Hassibi, A. (2007). A tutorial on geometric programming. Optimization and engineering, 8(1), 67–127.CrossRefMATHMathSciNetGoogle Scholar
  2. [Cederbaum 92]
    I. Cederbaum, I. Koren and S. Wimer, “Balanced block spacing for VLSI layout,” Discrete Applied Mathematics, Vol. 40, Issue 3, 1992, pp. 308–318.CrossRefMathSciNetGoogle Scholar
  3. [Chaudhary 92]
    K. Chaudhary and M. Pedram, “A near optimal algorithm for technology mapping minimizing area under delay constraints”, Proceeding of Design Automation Conference, July 1992, pp. 492–498.Google Scholar
  4. [Chen 05]
    R. Chen and H. Zhou, “An Efficient Data Structure for Maxplus Merge in Dynamic Porgramming”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, pp. 3004–3009.Google Scholar
  5. [Cheng 00]
    C.-K. Cheng, J. Lillis, S. Lin and N.H. Chang, Interconnect Analysis and Synthesis, John Wiley Press, 2000Google Scholar
  6. [Cong 94]
    J. Cong and C. Koh, “Simultaneous Driver and Wire Sizing for Performance and Power Optimization”, IEEE Transactions on VLSI, vol. 2, no. 4, 1994Google Scholar
  7. [Garey 79]
    M. R. Garey and D. S. Johnson, Computers and Intractability, Freeman, 1979.Google Scholar
  8. [Hodges 04]
    D. A. Hodges, H. G. Jackson and R. A. Saleh, Analysis and Design of Digital Integrated Circuits, McGraw Hill, 3rd edition, 2004.Google Scholar
  9. [Li 93]
    W-N. Li, A. Lim, P. Agrawal and S. Sahani, “On circuit implementation problem”, IEEE TCAD, 1993, pp. 1147–1156.Google Scholar
  10. [Moiseev 09]
    16. K. Moiseev, A. Kolodny and S. Wimer, “Power-Delay Optimization in VLSI Microprocessors by Wire Spacing,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14, Issue 4 (August 2009), Article No. 55, 2009, ISSN: 1084–4309.Google Scholar
  11. [Noble 88]
    B. Noble and J.W. Daniel, Applied linear algebra, Prentice-Hall International, 3rd edition, 1988.Google Scholar
  12. [Shi 03]
    W. Shi and Z. Li, “An O(nlogn) time algorithm for optimal buffer insertion”, Proceedings of Design Automation Conference, 2003, pp. 580–585Google Scholar
  13. [van Ginnekken 90]
    L.P.P.P van Ginneken, “Buffer Placement in Distributed RC-Tree Networks for Minimal Elmore Delay,” Proc. International Symposium on Circuits and Systems, pp. 865–868, 1990.Google Scholar
  14. [Webb 08]
    C. Webb, “45 nm Design for Manufacturing”, Intel Technology Journal, 2008Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Konstantin Moiseev
    • 1
  • Avinoam Kolodny
    • 2
  • Shmuel Wimer
    • 3
  1. 1.IntelHaifaIsrael
  2. 2.TechnionHaifaIsrael
  3. 3.Bar-Ilan UniversityRamat-GanIsrael

Personalised recommendations